公开(公告)号：WO2013101201A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068151

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  ZIAKAS, Dimitrios ,  CAI, Zhong-Ning

Inventor： ZIAKAS, Dimitrios ,  CAI, Zhong-Ning

IPC: G06F12/00 ,  G06F13/14 ,  G06F13/16

CPC classification number: G06F3/0619 ,  G06F3/0646 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F2212/1028 ,  G06F2212/205 ,  Y02D10/13

Abstract: Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.

Abstract translation: 实现具有易失性存储器和非易失性存储器的多级存储器系统的系统和方法。 归属代理可以控制对易失性主存储器和非易失性第二级存储器的存储器访问。 第二级存储器可以包括主存储器。 在一个实施例中，归属代理可以被配置为在低功率状态下管理存储器系统。 在低功率状态下，可以关闭易失性存储器，并将非易失性存储器用作唯一的本地存储器。 在一个实施例中，归属代理可以被配置为通过恢复在本地保存在第二级存储器中的数据来管理主存储器的错误恢复。 在一个实施例中，多个核可以访问第二级存储器。

公开(公告)号：WO2006031414A2

公开(公告)日：2006-03-23

申请号：PCT/US2005/030444

申请日：2005-08-26

Applicant: INTEL CORPORATION ,  GILBERT, Jeffrey ,  CAI, Zhong-Ning ,  LIU, Yen-Cheng ,  SISTLA, Krishnakanth

Inventor： GILBERT, Jeffrey ,  CAI, Zhong-Ning ,  LIU, Yen-Cheng ,  SISTLA, Krishnakanth

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815

Abstract: Preventing cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

Abstract translation: 防止微处理器和/或计算机系统中的缓存冲突。 更具体地，本发明的实施例涉及一种管理处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。

公开(公告)号：WO2013081580A1

公开(公告)日：2013-06-06

申请号：PCT/US2011/062317

申请日：2011-11-29

Applicant: INTEL CORPORATION ,  SAFRANEK, Robert J. ,  BLANKENSHIP, Robert G. ,  CAI, Zhong-Ning

Inventor： SAFRANEK, Robert J. ,  BLANKENSHIP, Robert G. ,  CAI, Zhong-Ning

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/16 ,  G06F13/1663 ,  G06F13/40 ,  G06F13/4004 ,  G06F13/4022

Abstract: Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route -back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.

Abstract translation: 用于实现原始内存事务的方法，系统和装置。 SoC配置有耦合在一起的多个节点，形成环形互连。 处理核心和存储器高速缓存组件可操作地耦合到并位于相应节点处。 存储器高速缓存组件包括作为分布式LLC操作的多个最后级别缓存（LLC）和用于支持相干存储器事务的多个归属代理和高速缓存代理。 Route-Back表用于使用便于在链接接口节点和存储器控制器之间进行数据传输的代理实现的嵌入式路由数据对内存事务请求进行编码。 因此，与原始存储器事务相对应的存储器请求数据可以使用无头段分组路由回请求实体。