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21 条记录 (耗时 0.009 秒)

    VIRTUALIZED COMMUNICATION SOCKETS FOR MULTI-FLOW ACCESS TO MESSAGE CHANNEL INFRASTRUCTURE WITHIN CPU
    2.
    发明申请
    VIRTUALIZED COMMUNICATION SOCKETS FOR MULTI-FLOW ACCESS TO MESSAGE CHANNEL INFRASTRUCTURE WITHIN CPU 审中-公开
    用于多CPU访问消息通道基础架构的虚拟通信插座

    公开(公告)号：WO2014058759A1

    公开(公告)日：2014-04-17

    申请号：PCT/US2013/063647

    申请日：2013-10-07

    申请人： INTEL CORPORATION ,  BORKOWSKI, Dan G. ,  SISTLA, Krishnakanth V.

    发明人： BORKOWSKI, Dan G. ,  SISTLA, Krishnakanth V.

    IPC分类号： G06F13/14 ,  G06F13/36

    CPC分类号： G06F9/546 ,  G06F9/544 ,  G06F9/545 ,  G06F13/4059

    摘要： A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction "behind the scenes". The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

    摘要翻译： 消息信道优化方法和系统使得能够对基于处理器的系统的CPU内的消息信道基础设施进行多流访问。 用户（pcode）使用虚拟通道提交消息通道事务，消息通道驱动程序处理事务“幕后”。 因此，消息通道驱动器允许用户继续处理，而不必阻止其他事务被处理。 消息通道驱动程序将立即或在将来的某个时间处理每个事务。 消息信道优化方法和系统对于涉及消息信道事务以及非消息信道事务的任务是有用的。

    PROVIDING AN INCLUSIVE SHARED CACHE AMONG MULTIPLE CORE-CACHE CLUSTERS
    4.
    发明申请
    PROVIDING AN INCLUSIVE SHARED CACHE AMONG MULTIPLE CORE-CACHE CLUSTERS 审中-公开

    公开(公告)号：WO2009018005A3

    公开(公告)日：2009-02-05

    申请号：PCT/US2008/070671

    申请日：2008-07-21

    申请人： INTEL CORPORATION ,  SISTLA, Krishnakanth

    发明人： SISTLA, Krishnakanth

    IPC分类号： G06F12/00

    摘要： In one embodiment, the present invention includes a method for receiving requested data from a system interconnect interface in a first scalability agent of a multi-core processor including a plurality of core-cache clusters, storing the requested data in a line of a local cache of a first core-cache cluster including a requestor core, and updating a cluster field and a core field in a vector of a tag array for the line. Other embodiments are described and claimed.

    MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS
    5.
    发明申请
    MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS 审中-公开
    用于协调无障碍和集群系统中的空闲电源管理的主从QPI协议

    公开(公告)号：WO2013165357A1

    公开(公告)日：2013-11-07

    申请号：PCT/US2012/035827

    申请日：2012-04-30

    申请人： INTEL CORPORATION ,  GARG, Vivek ,  SISTLA, Krishnakanth ,  BLANKENSHIP, Robert ,  MULLA, Dean ,  BORKOWSKI, Daniel G. ,  CONRAD, Shaun ,  SRINIVASA, Ganapati

    发明人： GARG, Vivek ,  SISTLA, Krishnakanth ,  BLANKENSHIP, Robert ,  MULLA, Dean ,  BORKOWSKI, Daniel G. ,  CONRAD, Shaun ,  SRINIVASA, Ganapati

    IPC分类号： G06F1/32 ,  G06F15/80 ,  G06F13/14

    CPC分类号： G06F1/3203 ,  G06F1/3234 ,  Y02D50/20

    摘要： Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner. Communications between the entities is facilitated using messages transported over existing interconnects and corresponding protocols, enabling the benefits associated with the disclosed embodiments to be implemented using existing designs.

    摘要翻译： 在无缝和集群系统中实现协调空闲电源管理的方法，设备和系统。 在诸如服务器平台的无胶纸系统中的用于促进协调包间歇功率状态的组件包括一个插座（即，处理器）中的主实体和参与电力管理协调的每个插座中的从实体。 每个从机从各种来源收集空闲状态输入，当插座内核足够空闲时，它要求主机进入更深的空闲电源状态。 主机响应于从机请求来协调全局功率管理操作，包括向所有从机广播具有目标延迟的命令，以允许处理器以协调的方式进入降低的功率（即空闲）状态。 使用通过现有互连和相应协议传输的消息来促进实体之间的通信，从而能够使用现有设计实现与公开的实施例相关联的益处。

    DYNAMIC POWER LIMIT SHARING IN A PLATFORM
    10.
    发明申请
    DYNAMIC POWER LIMIT SHARING IN A PLATFORM 审中-公开
    动态功率限制在平台中共享

    公开(公告)号：WO2013147801A1

    公开(公告)日：2013-10-03

    申请号：PCT/US2012/031249

    申请日：2012-03-29

    申请人： INTEL CORPORATION ,  VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

    发明人： VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

    摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

    摘要翻译： 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高的峰值性能。