公开(公告)号：WO2014055520A1

公开(公告)日：2014-04-10

申请号：PCT/US2013/062867

申请日：2013-10-01

Applicant: KNOWLES ELECTRONICS, LLC

Inventor： JENNINGS, Michael ,  STEIN, Craig ,  BADILLO, Dean

IPC: H03K19/0185

CPC classification number: H03F3/16 ,  H03F3/185 ,  H04R2410/00 ,  H04R2410/03 ,  H04R2410/07

Abstract: A single-stage buffer apparatus includes a first transistor, a second transistor, and a high pass filter network. The first transistor is configured to receive an input signal from a microphone. The second transistor is configured to operate as a cascode transistor. The high pass filter network is coupled to the first transistor and the second transistor. The second transistor electrically decouples the first transistor from an output of the single-stage buffer apparatus. A gate terminal of the second transistor is driven by the high-pass filter network, and the high-pass filter network is driven by the first transistor.

Abstract translation: 单级缓冲装置包括第一晶体管，第二晶体管和高通滤波器网络。 第一晶体管被配置为从麦克风接收输入信号。 第二晶体管被配置为作为共源共栅晶体管工作。 高通滤波器网络耦合到第一晶体管和第二晶体管。 第二晶体管将第一晶体管与单级缓冲装置的输出电耦合。 第二晶体管的栅极端子由高通滤波器网络驱动，高通滤波器网络由第一晶体管驱动。

公开(公告)号：WO2017065965A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/053728

申请日：2016-09-26

Applicant: KNOWLES ELECTRONICS, LLC

Inventor： JENNINGS, Michael ,  BADILLO, Dean ,  STEIN, Craig

IPC: H03F1/30 ,  H03F3/181 ,  H04R3/00

CPC classification number: H03F1/0205 ,  H03F1/30 ,  H03F1/32 ,  H03F3/04 ,  H03F3/181 ,  H03F2200/03 ,  H03F2200/18 ,  H03F2200/228 ,  H03F2200/42 ,  H03F2200/453 ,  H03F2200/471 ,  H03F2200/555 ,  H03F2200/78 ,  H04R3/00 ,  H04R2410/00

Abstract: A direct current (DC) bias maintenance circuit operably couples to the input of a primary amplifier. The DC bias maintenance circuit employs feedback to maintain the desired DC bias but lacks any coupling to the output of the primary amplifier. By one approach the DC bias maintenance circuit includes a secondary amplifier that replicates at least some near real-time performance characteristics of the primary amplifier. For example, the secondary amplifier can replicate at least certain DC properties of the primary amplifier such that DC-based changes appearing at the output of the primary amplifier are mirrored at an output of the secondary amplifier notwithstanding a lack of any coupling between the output of the primary amplifier and the DC bias maintenance circuit.

Abstract translation: 直流（DC）偏压维持电路可操作地耦合到主放大器的输入。 直流偏置维持电路采用反馈来保持所需的直流偏置，但缺少与主放大器输出的任何耦合。 通过一种方法，DC偏置维持电路包括复制主放大器的至少一些接近实时性能特性的次级放大器。 例如，次级放大器可以复制初级放大器的至少某些DC属性，使得出现在初级放大器的输出处的基于DC的变化在次级放大器的输出处被镜像，尽管缺少输出端之间的任何耦合 主放大器和直流偏置维护电路。

公开(公告)号：WO2015065523A1

公开(公告)日：2015-05-07

申请号：PCT/US2014/038598

申请日：2014-05-19

Applicant: KNOWLES ELECTRONICS, LLC

Inventor： JENNINGS, Michael ,  STEIN, Craig ,  BADILLO, Dean

IPC: H03F3/185 ,  H04R3/00

CPC classification number: H04R3/002 ,  G10L21/0208 ,  H04R1/08 ,  H04R3/00 ,  H04R3/02 ,  H04R25/50 ,  H04R2201/003

Abstract: A buffer is coupled to an acoustic motor. The buffer has an input and an output. The input has an input voltage and the output has an output voltage. The buffer is coupled to a load. The buffer includes an input transistor and push-pull transistor circuitry. The input transistor has a gate, a source, and a drain, a gate-to-source capacitance, and an area. The push-pull transistor circuitry is coupled to the input transistor. Under a first set of operating conditions, the gate to source voltage of the input transistor remains constant and the output voltage is a buffered copy of the input voltage. Under a second set of operating conditions, the push-pull transistor circuitry selectively sinks or sources additional current to the load so that linearity of buffer operation is provided. A gate-to-drain capacitance of the input transistor is buffered allowing the area of the input transistor to be increased without reducing the gain of the motor.

Abstract translation: 缓冲器耦合到声学电动机。 缓冲区有一个输入和一个输出。 输入具有输入电压，输出具有输出电压。 缓冲器耦合到一个负载。 该缓冲器包括输入晶体管和推挽晶体管电路。 输入晶体管具有栅极，源极和漏极，栅极 - 源极电容和区域。 推挽晶体管电路耦合到输入晶体管。 在第一组工作条件下，输入晶体管的栅极至源极电压保持恒定，输出电压为输入电压的缓冲副本。 在第二组工作条件下，推挽晶体管电路有选择地将负载的电流吸收或发送到负载，从而提供缓冲器操作的线性。 输入晶体管的栅极到漏极电容被缓冲，允许输入晶体管的面积增加而不降低电动机的增益。