公开(公告)号：WO2016205675A1

公开(公告)日：2016-12-22

申请号：PCT/US2016/038115

申请日：2016-06-17

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  MICKEY, David ,  KRIS, Bryan

IPC: G06F15/167

CPC classification number: G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F15/167

Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

Abstract translation: 单片微控制器具有主核和至少一个从核。 主核心由主系统时钟计时，从核心由从系统时钟计时，并且其中每个核心分别与多个外围设备相关联以形成主微控制器和从微控制器。 在主微控制器和从属微控制器之间提供通信接口，其中通信接口具有多个可配置方向性数据寄存器，与流控制逻辑耦合，流控制逻辑可配置为向多个可配置数据寄存器中的每一个分配方向。

公开(公告)号：WO2013040280A1

公开(公告)日：2013-03-21

申请号：PCT/US2012/055268

申请日：2012-09-14

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  KRIS, Bryan ,  CATHERWOOD, Michael

Inventor： KRIS, Bryan ,  CATHERWOOD, Michael

IPC: G06F13/00 ,  G06F15/78

CPC classification number: G06F3/05 ,  G06F1/04 ,  G06F15/7814

Abstract: A microcontroller includes a central processing unit (CPU); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal.

Abstract translation: 微控制器包括中央处理单元（CPU）; 多个外围单元; 以及外围触发发生器，其包括用户可编程状态机，其中所述外围触发发生器被配置为接收多个输入信号，并且可编程以根据所述输入信号中的至少一个自动化定时功能并且生成至少一个输出信号。

公开(公告)号：WO2002099634A1

公开(公告)日：2002-12-12

申请号：PCT/US2002/016970

申请日：2002-05-30

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W. ,  PYSKA, Michael ,  CONNER, Joshua, M.

IPC: G06F9/38

CPC classification number: G06F9/342 ,  G06F9/30185 ,  G06F9/345 ,  G06F12/0284 ,  G06F12/109

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Abstract translation: 提供了一种处理器，其具有数据存储器，该数据存储器可以以一种模式被寻址为双存储器空间，并且在另一种模式下可以被寻址为单个线性存储器空 当处理DSP指令时，存储器可能允许从数据存储器获取双重并发操作数。 然后，存储器可以动态地允许相同的存储器作为用于非DSP指令的单个线性存储器地址空间被访问。

公开(公告)号：WO2016176585A1

公开(公告)日：2016-11-03

申请号：PCT/US2016/030141

申请日：2016-04-29

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  MICKEY, David

IPC: G06F9/30

CPC classification number: G06F9/462 ,  G06F9/4401

Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

Abstract translation: 集成电路装置具有包括数字信号处理（DSP）引擎和多个上下文的第一中央处理单元，每个上下文具有具有多个寄存器和DSP上下文的CPU上下文，其中DSP上下文具有控制位和 多个DSP寄存器，其中在集成电路器件复位之后，将所有DSP上下文的控制位链接在一起，使得写入DSP上下文的控制位的数据被写入所有其它DSP上下文的相应控制位，并且仅 在上下文切换到另一个上下文并修改另一个DSP上下文的至少一个控制位之后，另一个上下文的控制位从链路被切断，以形成DSP上下文的独立控制位。

公开(公告)号：WO2011091017A1

公开(公告)日：2011-07-28

申请号：PCT/US2011/021689

申请日：2011-01-19

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  SIMMONS, Michael ,  CATHERWOOD, Michael

Inventor： SIMMONS, Michael ,  CATHERWOOD, Michael

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3287 ,  Y02D10/171

Abstract: An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status.

Abstract translation: 集成电路装置控制用于感测过程变量的外部设备的上电，独立于集成电路器件是否处于低功耗睡眠模式。 一旦外部设备运行，集成设备即使在仍处于低功耗睡眠模式的状态下，也会对外部设备的过程变量状态进行采样。 在低功率睡眠模式期间操作的低功率定时电路控制外部设备的上电并对其过程变量状态进行采样。 在采用过程变量状态的采样之后，根据采样的过程变量状态确定，集成电路器件可以在适当时从低功率睡眠模式退出到操作模式。

公开(公告)号：WO2002099647A1

公开(公告)日：2002-12-12

申请号：PCT/US2002/016705

申请日：2002-05-29

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael

IPC: G06F12/00

CPC classification number: G06F9/3802 ,  G06F9/3861 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1416

Abstract: A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.

Abstract translation: 处理器具有提供哈佛架构的处理速度优势的架构，但是不需要两个单独的外部存储器，以便扩展数据存储器和程序指令存储器。 处理器具有单独的程序存储器空间和数据存储器空间，但是提供将程序存储空间的至少一部分映射到数据存储空间的能力。 这允许处理的大多数程序指令获得同时程序指令和数据访问的速度优势。 它还允许程序存储空间和数据存储空间从外部扩展到处理器，只使用一个包含程序指令和数据的外部存储器。 处理器包括可操作以存储程序指令和数据的程序存储空间，可操作以存储数据的数据存储空间，以及可操作以将程序存储器空间的至少一部分映射到数据存储空间的映射电路。 程序存储空间可能在处理器内部。 处理器还可以包括页面寄存器，其可操作以指定映射到数据存储器空间的程序存储器空间的位置。

公开(公告)号：WO2016205675A9

公开(公告)日：2016-12-22

申请号：PCT/US2016/038115

申请日：2016-06-17

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  MICKEY, David ,  KRIS, Bryan

IPC: G06F15/167

Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

公开(公告)号：WO2016176593A1

公开(公告)日：2016-11-03

申请号：PCT/US2016/030159

申请日：2016-04-29

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  MICKEY, David ,  KRIS, Bryan ,  WILKIE, Calum ,  SACHS, Jason ,  REITER, Andreas

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。

公开(公告)号：WO2016161409A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/025799

申请日：2016-04-03

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  IVEY, Brant ,  RANGARAJAN, Sankar

IPC: G06F11/22

CPC classification number: G06F11/263 ,  G06F11/10 ,  G06F11/2205 ,  G06F11/2215

Abstract: Systems and methods for a run-time error correction code ("ECC") error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

Abstract translation: 公开了用于硬件验证的运行时纠错码（“ECC”）错误注入方案的系统和方法。 系统和方法包括配置读取路径以内部转发读取数据，以及经由读取故障注入逻辑将至少一个故障位注入转发的读取数据。 系统和方法还可以包括配置写入路径以内部转发写入数据，以及经由写入故障注入逻辑将至少一个故障位注入转发的写入数据。

公开(公告)号：WO2002099633A1

公开(公告)日：2002-12-12

申请号：PCT/US2002/016706

申请日：2002-05-29

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael ,  TRIECE, Joseph, W.

IPC: G06F9/32

CPC classification number: G06F9/30065

Abstract: A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruction may include an address of a register which holds the loop count value. The instruction immediately following the repeat instruction is the target instruction for repetition. The processing includes repeating execution of the target instruction according to the loop count value in a low processor cycle overhead manner. The processing may also include handling interrupts during repeat instruction processing in a low-overhead manner during the initial call of the interrupt service routine as well as upon returning from the interrupt service routine.

Abstract translation: 提供了一种处理可中断重复指令的处理器。 重复指令可以包括指定与循环要重复的次数相对应的循环计数值的立即操作数。 或者，重复指令可以包括保存循环计数值的寄存器的地址。 重复指令之后的指令是重复的目标指令。 该处理包括以低处理器周期开销方式根据循环计数值重复执行目标指令。 处理还可以包括在中断服务程序的初始调用期间以及从中断服务程序返回时以低开销方式在重复指令处理期间处理中断。