公开(公告)号：WO1997023045A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020677

申请日：1996-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  CLOUD, Eugene, H.

IPC: H03K19/017

CPC classification number: H03K19/01721

Abstract: An asynchronous self-adjusting circuit (20) includes an input circuit (22) receiving an input signal and providing an output signal. The input circuit (22) starts to switch the output signal to a first logic level based on the level of the input signal reaching a falling edge adjustable trip point, and starts to switch the output signal to a second logic level base on the level of the input signal reaching a rising edge adjustable trip point. A control circuit (24) dynamically and asynchronously adjusts the falling and rising edge adjustable trip points as a function of a previous value of the input signal to permit the asynchronous self-adjusting circuit to respond quickly to changes in the input signal without causing oscillation of the output signal by asynchronously controlling when the output signal is permitted to again switch logic states one the output signal switches logic states.

Abstract translation: 异步自调整电路（20）包括接收输入信号并提供输出信号的输入电路（22）。 基于输入信号的电平达到下降沿可调跳变点，输入电路（22）开始将输出信号切换到第一逻辑电平，并且基于电平的等级开始将输出信号切换到第二逻辑电平 输入信号达到上升沿可调跳闸点。 控制电路（24）根据输入信号的先前值动态地和异步地调整下降沿和上升沿可调跳变点，以允许异步自调节电路快速响应输入信号的变化而不引起振荡 输出信号通过异步地控制何时允许输出信号再次切换逻辑状态，一个输出信号切换逻辑状态。

公开(公告)号：WO1997008702A1

公开(公告)日：1997-03-06

申请号：PCT/US1996014001

申请日：1996-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CLOUD, Eugene, H. ,  WILLIAMS, Brett, L. ,  MANNING, Troy, A.

IPC: G11C07/00

CPC classification number: G11C7/1063 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/4076

Abstract: A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.

Abstract translation: 描述了包括用于存储数据的存储单元的存储器电路。 存储器电路可以由诸如微处理器或核心逻辑芯片组的外部系统读取或写入。 微处理器向存储器电路提供存储单元地址数据，并且可以请求在通信线路上输出数据以从中读出数据。 存储器电路通过提供有效的输出数据信号来减少读取存储在存储器中的数据所需的时间。 有效输出数据信号表示耦合到通信线路的数据已经稳定，因此是有效的。 描述了用于产生信号的不同的有效输出数据信号和触发电路。