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    DIFFERENTIAL INPUT BUFFER BIAS PULSER
    2.
    发明申请
    DIFFERENTIAL INPUT BUFFER BIAS PULSER 审中-公开

    公开(公告)号：WO2002069496A3

    公开(公告)日：2002-09-06

    申请号：PCT/US2002/002760

    申请日：2002-02-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： WRIGHT, Jeffrey, P. ,  WILSON, Alan, J.

    IPC: H03K5/24

    Abstract: An integrated circuit clock buffer is described which includes a pulser circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The pulser circuit includes a delay element having an output node coupled to the input node of an inverter. The delay element and inverter are coupled between a first and second transistor. The buffer circuit generates non-skewed internal clock signals.

    SHARED COUNTER
    3.
    发明申请
    SHARED COUNTER 审中-公开
    共享计数器

    公开(公告)号：WO1997028605A1

    公开(公告)日：1997-08-07

    申请号：PCT/US1997000948

    申请日：1997-01-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  ZHENG, Hua

    IPC: H03K21/00

    CPC classification number: H03K21/00

    Abstract: A shared counter (32) performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit (21) selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit (32) provides counter output data based on the counter initialization data. An output circuit (35) provides the counter output data to K destination circuits in the electronic circuit. The output circuit (35) provides only one of the K destination circuits with the counter output data at a given time.

    Abstract translation: 共享计数器（32）在诸如存储器集成电路的电子电路中执行多个计数功能。 输入选择电路（21）在给定时间选择M个输入数据组中的一个作为计数器初始化数据提供。 计数器电路（32）基于计数器初始化数据提供计数器输出数据。 输出电路（35）将计数器输出数据提供给电子电路中的K个目标电路。 在给定时间，输出电路（35）仅提供K个目标电路中的一个与计数器输出数据。

    ASYNCHRONOUS SELF-ADJUSTING INPUT CIRCUIT
    4.
    发明申请
    ASYNCHRONOUS SELF-ADJUSTING INPUT CIRCUIT 审中-公开
    异步自调节输入电路

    公开(公告)号：WO1997023045A1

    公开(公告)日：1997-06-26

    申请号：PCT/US1996020677

    申请日：1996-12-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  CLOUD, Eugene, H.

    IPC: H03K19/017

    CPC classification number: H03K19/01721

    Abstract: An asynchronous self-adjusting circuit (20) includes an input circuit (22) receiving an input signal and providing an output signal. The input circuit (22) starts to switch the output signal to a first logic level based on the level of the input signal reaching a falling edge adjustable trip point, and starts to switch the output signal to a second logic level base on the level of the input signal reaching a rising edge adjustable trip point. A control circuit (24) dynamically and asynchronously adjusts the falling and rising edge adjustable trip points as a function of a previous value of the input signal to permit the asynchronous self-adjusting circuit to respond quickly to changes in the input signal without causing oscillation of the output signal by asynchronously controlling when the output signal is permitted to again switch logic states one the output signal switches logic states.

    Abstract translation: 异步自调整电路（20）包括接收输入信号并提供输出信号的输入电路（22）。 基于输入信号的电平达到下降沿可调跳变点，输入电路（22）开始将输出信号切换到第一逻辑电平，并且基于电平的等级开始将输出信号切换到第二逻辑电平 输入信号达到上升沿可调跳闸点。 控制电路（24）根据输入信号的先前值动态地和异步地调整下降沿和上升沿可调跳变点，以允许异步自调节电路快速响应输入信号的变化而不引起振荡 输出信号通过异步地控制何时允许输出信号再次切换逻辑状态，一个输出信号切换逻辑状态。

    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    6.
    发明申请
    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 审中-公开
    基于命令信号和操作状态解码命令的系统和方法

    公开(公告)号：WO2006118788A2

    公开(公告)日：2006-11-09

    申请号：PCT/US2006/014650

    申请日：2006-04-17

    Applicant: MICRON TECHNOLOGY, INC. ,  JANZEN, Jeffrey, W. ,  KEETH, Brent ,  WRIGHT, Jeffrey, P. ,  CULLUM, James, S.

    Inventor： JANZEN, Jeffrey, W. ,  KEETH, Brent ,  WRIGHT, Jeffrey, P. ,  CULLUM, James, S.

    IPC: G06F13/00

    CPC classification number: G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    Abstract translation: 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态进行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    AUTO REFRESH TO SPECIFIED BANK
    7.
    发明申请
    AUTO REFRESH TO SPECIFIED BANK 审中-公开
    自动刷新指定银行

    公开(公告)号：WO1997030453A1

    公开(公告)日：1997-08-21

    申请号：PCT/US1997002652

    申请日：1997-02-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  ZHENG, Hua

    IPC: G11C11/406

    CPC classification number: G11C11/406

    Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an auto-refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.

    Abstract translation: 诸如同步动态随机存取存储器或同步图形随机存取存储器的同步随机存取存储器响应命令信号并且包括多个存储体存储器阵列。 命令解码器/控制器响应于命令信号，以在第一系统时钟周期内启动控制对多个存储体存储器阵列中指定的一个的自动刷新操作的自动刷新命令。

    MEMORY DEVICE WITH MULTIPLE INTERNAL BANKS AND STAGGERED COMMAND EXECUTION
    8.
    发明申请
    MEMORY DEVICE WITH MULTIPLE INTERNAL BANKS AND STAGGERED COMMAND EXECUTION 审中-公开
    具有多个内部银行的存储设备和标记的执行

    公开(公告)号：WO1997024727A1

    公开(公告)日：1997-07-10

    申请号：PCT/US1996020784

    申请日：1996-12-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  RYAN, Kevin, J. ,  WRIGHT, Jeffrey, P.

    IPC: G11C07/00

    CPC classification number: G11C7/1072 ,  G11C7/1039

    Abstract: In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a time-staggered basis. In an eight bank embodiment, activation of a selected row is first initiated in Bank0 by registration of an ACTIVE command and a coincident row address. One system clock cycle later, activation of the selected row is initiated in Bank1, and so on until activation of the selected row is initiated in Bank7 seven clock cycles after the intial registration of the command. A READ or WRITE command and coincident column address can be applied after the activation time limit has been met for the selected row in Bank0. The READ or WRITE command then affects successive banks in the above-described time staggered manner. Similarly, a PRECHARGE command can be applied when the read latency or write recovery time limit has been met for Bank0, and this command is executed in a time staggered manner in the successive banks. In a four bank embodiment, command registration and execution is staggered every two successive system clock cycles.

    Abstract translation: 在诸如面向页面的同步动态随机存取存储器件（SDRAM）的存储器件中，存储器阵列和相关联的电路被分成多个内部限定的电路组。 应用于存储器设备的命令和地址对所有内部银行都是相同的，但是在时间上是交错的。 在八个银行实施例中，首先通过注册ACTIVE命令和一致的行地址来在Bank0中启动所选行的激活。 稍后一个系统时钟周期，在Bank1中启动所选行的激活，依此类推，直到在初始注册命令后七个时钟周期内在Bank7中启动所选行。 在Bank0中所选行的激活时间限制满足后，可以应用READ或WRITE命令和重合列地址。 READ或WRITE命令以上述时间交错的方式影响连续的存储体。 类似地，当Bank0的读延迟或写恢复时间限制已被满足时，可以应用PRECHARGE命令，并且该命令以连续存储体中的交错方式执行。 在四组实施例中，命令注册和执行每两个连续的系统时钟周期交错。

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