公开(公告)号：WO2019040495A1

公开(公告)日：2019-02-28

申请号：PCT/US2018/047328

申请日：2018-08-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MILLS, Duane R. ,  FACKENTHAL, Richard E.

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/02

Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.

公开(公告)号：WO2019046104A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/047790

申请日：2018-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FACKENTHAL, Richard E. ,  VIMERCATI, Daniele ,  MILLS, Duane R.

IPC: G11C11/22

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

公开(公告)号：WO2023009333A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/037309

申请日：2022-07-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CARMAN, Eric S. ,  RAMASWAMY, Durai Vishak Nirmal ,  FACKENTHAL, Richard E. ,  KARDA, Kamal M. ,  SARPATWARI, Karthik ,  LIU, Haitao ,  MILLS, Duane R. ,  CAILLAT, Christian

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/788

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated, from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：WO2022182838A1

公开(公告)日：2022-09-01

申请号：PCT/US2022/017653

申请日：2022-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  SARPATWARI, Karthik ,  RAMASWAMY, Durai Vishak Nirmal ,  CALDERONI, Alessandro ,  FACKENTHAL, Richard E. ,  MILLS, Duane R.

IPC: H01L27/108 ,  H01L29/78

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：WO2019027727A1

公开(公告)日：2019-02-07

申请号：PCT/US2018/043414

申请日：2018-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FACKENTHAL, Richard E. ,  MILLS, Duane R.

IPC: G06F12/02 ,  G11C16/34

Abstract: An example apparatus comprises a first portion of an array of memory cells, a second portion of the array of memory cells, a first register corresponding to the first portion, and a second register corresponding to the second portion. The first register is to indicate whether the first portion is to be wear leveled based on how often the first portion is or is to be accessed, and the second register is to indicate whether the second portion is to be wear leveled based on how often the second portion is or is to be accessed. The apparatus is to set the first or second register to indicate whether the first or second portion is to be wear leveled in response to a setup command. And the apparatus is to receive the setup command when the apparatus powers up.