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    METHODS OF INCORPORATING LEAKER DEVICES INTO CAPACITOR CONFIGURATIONS TO REDUCE CELL DISTURB, AND CAPACITOR CONFIGURATIONS INCORPORATING LEAKER DEVICES
    2.
    发明申请
    METHODS OF INCORPORATING LEAKER DEVICES INTO CAPACITOR CONFIGURATIONS TO REDUCE CELL DISTURB, AND CAPACITOR CONFIGURATIONS INCORPORATING LEAKER DEVICES 审中-公开

    公开(公告)号：WO2019118178A1

    公开(公告)日：2019-06-20

    申请号：PCT/US2018/062811

    申请日：2018-11-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： CHAVAN, Ashonita A. ,  COOK, Beth R. ,  NAHAR, Manuj ,  RAMASWAMY, Durai Vishak Nirmal

    IPC: H01L27/11502 ,  H01L27/06 ,  H01L23/485

    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

    A HYBRID MEMORY DEVICE
    3.
    发明申请
    A HYBRID MEMORY DEVICE 审中-公开
    混合存储设备

    公开(公告)号：WO2018044607A1

    公开(公告)日：2018-03-08

    申请号：PCT/US2017/047787

    申请日：2017-08-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： RYAN, Kevin J. ,  PRALL, Kirk D. ,  RAMASWAMY, Durai Vishak Nirmal ,  QUINN, Robert

    IPC: H01L27/108

    Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

    Abstract translation: 描述了用于混合存储器设备的方法，系统和设备。 混合存储器件可以包括在单个衬底或管芯上的易失性和非易失性存储器单元。 非易失性存储器单元可以具有铁电电容器，并且易失性存储器单元可以具有用于它们各自的逻辑存储部件的顺电或线性电介质电容器。 在一些示例中，易失性存储单元可以用作非易失性存储单元的高速缓存。 或者，非易失性存储单元可以用作易失性存储单元的备份。 通过将这两种类型的电池放置在单个裸片上而不是单独的裸片上，可以改进各种性能指标，包括与功耗和操作速度相关的指标。

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL
    4.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL 审中-公开

    公开(公告)号：WO2023076254A1

    公开(公告)日：2023-05-04

    申请号：PCT/US2022/047708

    申请日：2022-10-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： RAMASWAMY, Durai Vishak Nirmal ,  KARDA, Kamal M.

    IPC: H10B12/00 ,  H01L29/788 ,  H01L29/66

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGION
    5.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGION 审中-公开

    公开(公告)号：WO2021041558A1

    公开(公告)日：2021-03-04

    申请号：PCT/US2020/048021

    申请日：2020-08-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： SARPATWARI, Karthik ,  KARDA, Kamal M. ,  RAMASWAMY, Durai Vishak Nirmal ,  LIU, Haitao

    IPC: H01L27/108 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  G11C11/402

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

    INTEGRATED ASSEMBLIES HAVING TRANSISTOR BODY REGIONS COUPLED TO CARRIER-SINK-STRUCTURES; AND METHODS OF FORMING INTEGRATED ASSEMBLIES
    6.
    发明申请
    INTEGRATED ASSEMBLIES HAVING TRANSISTOR BODY REGIONS COUPLED TO CARRIER-SINK-STRUCTURES; AND METHODS OF FORMING INTEGRATED ASSEMBLIES 审中-公开

    公开(公告)号：WO2020181049A1

    公开(公告)日：2020-09-10

    申请号：PCT/US2020/021115

    申请日：2020-03-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  RAMASWAMY, Durai Vishak Nirmal ,  GAO, Yunfei ,  TANG, Sanh D. ,  PANDEY, Deepak Chandra

    IPC: H01L27/108

    Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

    SINGLE WORD LINE GAIN CELL
    7.
    发明申请
    SINGLE WORD LINE GAIN CELL 审中-公开

    公开(公告)号：WO2020139753A1

    公开(公告)日：2020-07-02

    申请号：PCT/US2019/067822

    申请日：2019-12-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  SARPATWARI, Karthik ,  RAMASWAMY, Durai Vishak Nirmal

    IPC: H01L27/108

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

    ARRAY OF CAPACITORS, ARRAY OF MEMORY CELLS, METHODS OF FORMING AN ARRAY OF CAPACITORS, AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS
    8.
    发明申请
    ARRAY OF CAPACITORS, ARRAY OF MEMORY CELLS, METHODS OF FORMING AN ARRAY OF CAPACITORS, AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS 审中-公开

    公开(公告)号：WO2020131324A1

    公开(公告)日：2020-06-25

    申请号：PCT/US2019/063306

    申请日：2019-11-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： CHHAJED, Sameer ,  CHAVAN, Ashonita, A. ,  FISCHER, Mark ,  RAMASWAMY, Durai Vishak Nirmal

    IPC: H01L27/06 ,  H01L27/07 ,  H01L27/08 ,  H01L27/10 ,  H01L49/02 ,  H01L27/11502

    Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally- spaced groups that individually comprise a plurality of horizontally -spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally -elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

    METHODS OF FORMING A DEVICE, AND RELATED DEVICES AND ELECTRONIC SYSTEMS
    10.
    发明申请
    METHODS OF FORMING A DEVICE, AND RELATED DEVICES AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：WO2020076764A1

    公开(公告)日：2020-04-16

    申请号：PCT/US2019/055111

    申请日：2019-10-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： SILLS, Scott E. ,  GANDHI, Ramanathan ,  RAMASWAMY, Durai Vishak Nirmal

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/02

    Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

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