公开(公告)号：WO2022160091A1

公开(公告)日：2022-08-04

申请号：PCT/CN2021/073765

申请日：2021-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Jiangang ,  ZHOU, Lei ,  HOEI, Jung Sheng ,  MUCHHERLA, Kishore Kumar ,  LIN, Qisong

IPC: G11C16/14

Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

公开(公告)号：WO2021183794A1

公开(公告)日：2021-09-16

申请号：PCT/US2021/021956

申请日：2021-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ALHUSSIEN, Abdelhakim ,  WU, Jiangang ,  SHUH, Karl D. ,  LIN, Qisong ,  HOEI, Jung Sheng

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G06F3/06 ,  G06F13/16

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

公开(公告)号：WO2021179164A1

公开(公告)日：2021-09-16

申请号：PCT/CN2020/078605

申请日：2020-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Jiangang ,  LIU, Jing Sang ,  CROWLEY, James, P. ,  LI, Yun

IPC: G06F3/06

Abstract: Methods, systems, and devices for data stream processing for maintaining queues for memory sub-systems are described. A number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system can be determined. Each queue can be associated with a respective priority level and can be configured to maintain a respective set of commands. A command can be assigned to the queue based on a number of commands included in the queue. One or more commands can be issued from the queues based on the respective priority levels of the queues.

公开(公告)号：WO2021179163A1

公开(公告)日：2021-09-16

申请号：PCT/CN2020/078604

申请日：2020-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Jiangang ,  LIU, Jingsang ,  LI, Yun ,  CROWLEY, James, P.

IPC: G06F3/06

Abstract: Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.

公开(公告)号：WO2021031205A1

公开(公告)日：2021-02-25

申请号：PCT/CN2019/102055

申请日：2019-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LIN, Qisong ,  RAYAPROLU, Vamsi Pavan ,  WU, Jiangang ,  RATNAM, Sampath K. ,  PARTHASARATHY, Sivagnanam ,  SHI, Shao Chun

IPC: G06F11/08 ,  G11C16/04

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command. A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.