公开(公告)号：WO2021031205A1

公开(公告)日：2021-02-25

申请号：PCT/CN2019/102055

申请日：2019-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LIN, Qisong ,  RAYAPROLU, Vamsi Pavan ,  WU, Jiangang ,  RATNAM, Sampath K. ,  PARTHASARATHY, Sivagnanam ,  SHI, Shao Chun

IPC: G06F11/08 ,  G11C16/04

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command. A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.

公开(公告)号：WO2021183794A1

公开(公告)日：2021-09-16

申请号：PCT/US2021/021956

申请日：2021-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ALHUSSIEN, Abdelhakim ,  WU, Jiangang ,  SHUH, Karl D. ,  LIN, Qisong ,  HOEI, Jung Sheng

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G06F3/06 ,  G06F13/16

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

公开(公告)号：WO2022160091A1

公开(公告)日：2022-08-04

申请号：PCT/CN2021/073765

申请日：2021-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Jiangang ,  ZHOU, Lei ,  HOEI, Jung Sheng ,  MUCHHERLA, Kishore Kumar ,  LIN, Qisong

IPC: G11C16/14

Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

公开(公告)号：WO2022133705A1

公开(公告)日：2022-06-30

申请号：PCT/CN2020/138229

申请日：2020-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： XU, Shuai ,  PICCARDI, Michele ,  MURALIDHARAN, Arvind ,  LEE, June ,  LIN, Qisong ,  STOLLER, Scott A. ,  SHEN, Jun

IPC: G11C5/00

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

公开(公告)号：WO2019157369A1

公开(公告)日：2019-08-15

申请号：PCT/US2019/017333

申请日：2019-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RATNAM, Sampath K. ,  RAYAPROLU, Vamsi Pavan ,  KAYNAK, Mustafa N. ,  PARTHASARATHY, Sivagnanam ,  MUCHHERLA, Kishore Kumar ,  NOWELL, Shane ,  FEELEY, Peter ,  LIN, Qisong

IPC: G06F11/16 ,  G06F3/06

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data i s provided to the other memory cell of the memory component.

公开(公告)号：WO2019156909A1

公开(公告)日：2019-08-15

申请号：PCT/US2019/016421

申请日：2019-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MUCHHERLA, Kishore Kumar ,  RAYAPROLU, Vamsi Pavan ,  FEELEY, Peter ,  RATNAM, Sampath K. ,  PARTHASARATHY, Sivagnanam ,  LIN, Qisong ,  NOWELL, Shane ,  KAYNAK, Mustafa N.

IPC: G11C29/52 ,  G11C29/02 ,  G06F11/10

Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.