公开(公告)号：WO1996017355A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015558

申请日：1995-11-30

申请人： MICRON TECHNOLOGY, INC.

发明人： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul

IPC分类号： G11C11/407

CPC分类号： G11C11/4076 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4096

摘要： An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.

摘要翻译： 集成电路存储器件具有两组NAND结构的存储器单元和用于同步地锁存控制，地址和数据信号的时钟输入。 通过使用双存储体架构和同步定时，对NAND结构中的顺序访问和恢复存储器位的时间延迟进行掩蔽。 NAND结构化存储器单元为高容量存储器件提供非常密集的存储器阵列。 驱动同步字线发生器的输入时钟信号提供对阵列的简化的高速访问。 一组随机访问存储寄存器临时存储阵列中的数据，并提供从存储器的每个存储体的整个数据页面的高速页面访问。 在同时打开或关闭另一个行中的一行时访问一个存储体的能力允许无限数量的高速顺序数据访问。

公开(公告)号：WO1995031042A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005537

申请日：1995-05-05

申请人： MICRON TECHNOLOGY, INC.

发明人： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul ,  MANNING, Troy

IPC分类号： H03K19/003

CPC分类号： H03K19/01742 ,  H03K19/00361

摘要： To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump (30) to continuously boost the input of an NMOS output circuit (24) so long as the output circuit is providing a logic high output signal. The NMOS output circuit (24) has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit (22) provides an oscillating digital signal to the boosting current pump (30). The pump (30) responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit (24) to compensate for the leakage current.

摘要翻译： 为了补偿由寄生电阻引起的泄漏电流，集成电路器件包括升压电流泵（30），只要输出电路提供逻辑高输出信号，就连续升压NMOS输出电路（24）的输入。 NMOS输出电路（24）具有用于接收输入信号的输入端和用于驱动至少一个输出信号线的输出端。 振荡电路（22）向升压电流泵（30）提供振荡数字信号。 泵（30）响应于振荡数字信号和输入信号处于两个预定状态之一，以在NMOS输出电路（24）的输入处提供额外的电流，以补偿漏电流。