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公开(公告)号：WO2003084161A1
公开(公告)日：2003-10-09
申请号：PCT/JP2002/003230
申请日：2002-03-29
IPC分类号： H04L25/02
CPC分类号： H03K19/01742 , H03K19/017581 , H04L25/028
摘要： ドライバ手段３０及び入力信号の現在のデータと過去のデータとを比較してドライバを制御するドライバ制御手段２０を備えるドライバ回路１０であって、ドライバ手段３０は複数の並列ドライバを有し、ドライバ制御手段２０は、入力信号の現在のデータと１サイクル前のデータとを比較して、異なる場合に複数の並列ドライバを動作させ、ドライバの駆動能力を増大させる。ドライバ制御手段２０は、さらに現在のデータを２サイクル前のデータと比較して、同じであるなら複数の並列ドライバの一部を動作させずに、駆動能力の増大の割合を低くすることができる。
摘要翻译： 一种驱动器电路（10），包括驱动器装置（30）和驱动器控制装置（20），用于通过比较当前数据和输入信号上的过去数据来控制驱动器。 驱动器装置（30）包括多个并行驱动器，并且驱动器控制装置（20）将输入信号和数据之间的当前数据与前一个周期进行比较，如果不同，则驱动多个并行驱动器，以增加驱动能力 的司机。 驱动器控制装置（20）进一步比较当前数据和两个循环之间的数据，如果相同，则驱动部分并行驱动器，从而可以降低驾驶能力的增加速率。
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公开(公告)号：WO1998042021A1
公开(公告)日：1998-09-24
申请号：PCT/JP1997000904
申请日：1997-03-19
发明人： HITACHI, LTD.
IPC分类号： H01L21/822
CPC分类号： H03K19/01742 , H01L27/0207
摘要： A third data circuit which is controlled by clock signals and works to accelerate the changes of signals on long-distance wiring after detecting the changes is provided near a second gate circuit, which receives the signal of a first gate circuit for driving the long-distance wiring, and between the first and second gate circuits. Therefore, the proportion of delay time, caused by the wiring resistance, in the critical path in a semiconductor integrated circuit is reduced and the speed of the critical path is increased. In addition, the operating frequency of the semiconductor integrated circuit can be improved.
摘要翻译： 在第二门电路附近提供由时钟信号控制并用于加速检测到变化后的长距离布线上的信号变化的第三数据电路，其接收用于驱动长距离的第一门电路的信号 布线，以及第一和第二门电路之间。 因此，在半导体集成电路的关键路径中由布线电阻引起的延迟时间的比例降低，并且关键路径的速度增加。 此外，可以提高半导体集成电路的工作频率。
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公开(公告)号：WO2007124304A3
公开(公告)日：2008-04-17
申请号：PCT/US2007066779
申请日：2007-04-17
申请人： ATMEL CORP , NG PHILIP S , SON JINSHU
发明人： NG PHILIP S , SON JINSHU
IPC分类号： G06F13/00
CPC分类号： H03K19/01721 , H03K19/01742
摘要： A dual-wire communications bus circuit (300), compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus (317) The bus has a first line for carrying data signals from a master device (201 ) to one or more slave devices (315A-315H) and a second line to carry a clock signal between the devices A pullup resistor (305, 311 ) is located in each part of the communications bus circuit, the pullup resistor (305) in the first part couples to the first line of the communications bus (317) and the pullup resistor (311) in the second part couples to the second line of the communications bus (317) To improve data throughput and reduce noise, an active pullup device (301A2-301 H2), working in conjunction with the pullup resistor (311 ), is located in each part of the communications bus circuit
摘要翻译： 与现有的双线总线协议兼容的双线通信总线电路（300）包括通信总线电路的第一和第二部分以耦合到通信总线（317）。总线具有用于承载数据信号的第一线 从主设备（201）到一个或多个从设备（315A-315H）和第二线路，以在设备之间携带时钟信号。上拉电阻器（305,311）位于通信总线电路的每个部分中， 第一部分中的上拉电阻（305）耦合到通信总线（317）的第一行，并且第二部分中的上拉电阻（311）耦合到通信总线（317）的第二行。为了提高数据吞吐量并减少 噪声，与上拉电阻（311）一起工作的有源上拉装置（301A2-301 H2）位于通信总线电路的每个部分
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公开(公告)号：WO2007124304A2
公开(公告)日：2007-11-01
申请号：PCT/US2007/066779
申请日：2007-04-17
申请人： ATMEL CORPORATION , NG, Philip, S. , SON, Jinshu
发明人： NG, Philip, S. , SON, Jinshu
IPC分类号： H03K19/003
CPC分类号： H03K19/01721 , H03K19/01742
摘要： A dual -wire communications bus circuit (300), compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit (300) to couple to a communications bus (317). The bus (317) has a first line for carrying data signals from a master device (201) to one or more slave devices (315A- 315H) and a second line to carry a clock signal between the devices (315A-315H). A pullup resistor (305, 311) is located in each part of the communications bus circuit (300); the pullup resistor (305) in the first part couples to the first line of the communications bus (317) and the pullup resistor (311) in the second part couples to the second line of the communications bus (317). To improve data throughput and reduce noise, an active pullup device (301A2-301H2), working in conjunction with the pullup resistor (311), is located in each part of the communications bus circuit (300), providing a high logic level on at least one of the communications bus lines.
摘要翻译： 与现有的双线总线协议兼容的双线通信总线电路（300）包括通信总线电路（300）的第一和第二部分，以耦合到通信总线（317）。 总线（317）具有用于将数据信号从主设备（201）传送到一个或多个从设备（315A-315H）的第一线路和用于在设备（315A-315H）之间传送时钟信号）的第二线路。 上拉电阻（305,311）位于通信总线电路（300）的每个部分中; 第一部分中的上拉电阻（305）耦合到通信总线（317）的第一行，并且第二部分中的上拉电阻（311）耦合到通信总线（317）的第二行。 为了提高数据吞吐量并降低噪声，与通信总线电路（300）的每个部分中位于与上拉电阻器（311）一起工作的有源上拉器件（301A2-301H2），提供高逻辑电平 至少有一条通信总线。
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公开(公告)号：WO1986001659A1
公开(公告)日：1986-03-13
申请号：PCT/US1985001600
申请日：1985-08-23
申请人： NCR CORPORATION
IPC分类号： H03K19/017
CPC分类号： H03K19/01742
摘要： A circuit for assisting transitions of a signal on a bus conductor (28) having a sensing means (44) connected to the bus conductor for determining if the bus conductor is in a first state or a second state, an assist element (30) for assisting transitions of a signal on the bus conductor between its first state and its second state responsive to clock pulses (61), and a logic circuit (32) connected to the sensing means (44) and the assist element (30) for enabling said assist element (30) when the transition of the said signal is from its first state to its second state during said clock pulses (61), and for disabling the assist element (30) when the signal transition is from its second state to its first state during said clock pulses (61).
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6.发明申请CAPACITIVE COUPLING TYPE LEVEL SHIFT CIRCUIT OF LOW POWER CONSUMPTION AND SMALL SIZE 审中-公开低功耗和小尺寸的电容耦合型电平转换电路
公开(公告)号：WO2007094571A1
公开(公告)日：2007-08-23
申请号：PCT/KR2007/000358
申请日：2007-01-22
申请人： IUCF-HYU , KWON, Oh-Kyoung
发明人： KWON, Oh-Kyoung
IPC分类号： H03K19/0175
CPC分类号： H03K19/01742 , H03K3/356121
摘要： Provided is a level shift circuit. The level shift circuit includes an inverter including a first transistor having a first polarity to which an input signal from an input port is applied through a gate and a second transistor having a second polarity which is an opposite polarity to the first polarity, the second transistor being connected in series to the first transistor between a positive source voltage and a negative source voltage and a connection node between the first and second transistors being an output port, a capacitor connected between a gate of the first transistor and a gate of the second transistor, and a voltage adjusting means for accurately adjusting a voltage applied to the gate of the second transistor according to an exact switching operation time of the second transistor, using a clock signal and an output port signal of the inverter. A stable and high-speed operation can be performed with a comparatively small size and low power consumption can be achieved.
摘要翻译： 提供了电平移位电路。 电平移位电路包括反相器，其包括具有第一极性的第一晶体管，来自输入端口的输入信号通过栅极施加到第一晶体管，第二晶体管具有与第一极性相反极性的第二极性，第二晶体管 在正源电压和负电源电压之间串联连接到第一晶体管，第一和第二晶体管之间的连接节点是输出端口，连接在第一晶体管的栅极和第二晶体管的栅极之间的电容器 以及电压调整装置，使用逆变器的时钟信号和输出端口信号，根据第二晶体管的精确切换操作时间来精确地调整施加到第二晶体管的栅极的电压。 可以以相对小的尺寸执行稳定和高速的操作，并且可以实现低功耗。
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公开(公告)号：WO1995031042A1
公开(公告)日：1995-11-16
申请号：PCT/US1995005537
申请日：1995-05-05
IPC分类号： H03K19/003
CPC分类号： H03K19/01742 , H03K19/00361
摘要： To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump (30) to continuously boost the input of an NMOS output circuit (24) so long as the output circuit is providing a logic high output signal. The NMOS output circuit (24) has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit (22) provides an oscillating digital signal to the boosting current pump (30). The pump (30) responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit (24) to compensate for the leakage current.
摘要翻译： 为了补偿由寄生电阻引起的泄漏电流，集成电路器件包括升压电流泵（30），只要输出电路提供逻辑高输出信号，就连续升压NMOS输出电路（24）的输入。 NMOS输出电路（24）具有用于接收输入信号的输入端和用于驱动至少一个输出信号线的输出端。 振荡电路（22）向升压电流泵（30）提供振荡数字信号。 泵（30）响应于振荡数字信号和输入信号处于两个预定状态之一，以在NMOS输出电路（24）的输入处提供额外的电流，以补偿漏电流。
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公开(公告)号：WO1983004149A1
公开(公告)日：1983-11-24
申请号：PCT/US1983000583
申请日：1983-04-21
IPC分类号： H03K19/003
CPC分类号： H03K19/0963 , H03K19/01742
摘要： An improvement in the basic domino circuit to reduce sensivity to leakage and noise. It basically involves addition of an unclocked small beta p-type pull-up transistor (17) in shunt with the clocked large beta p-type pull-up transistor (13) between the high power terminal and the output node (14) of each stage. This added transistor is operated with its gate so connected that it provides pull-up current to the output node during the evaluation phase when the large beta transistor is turned off.
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公开(公告)号：WO1981002361A1
公开(公告)日：1981-08-20
申请号：PCT/US1980000663
申请日：1980-05-22
申请人： MOSTEK CORP
发明人： MOSTEK CORP , WILSON D
IPC分类号： G11C11/40
CPC分类号： H03K19/01742 , G11C11/406
摘要： Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at an intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor (26) connected between the drain supply and a digit line (12) having a gate (28) connected to the source of a second transistor (30). The drain of the second transistor (30) is connected to a clocked source of potential at least one threshold above the drain supply. The gate (32) of the second transistor (30) is precharged to a potential near the drain supply voltage preferably concurrent with precharging of digit lines in the memory proper. A third transistor (34) is connected between the gate (32) of the second transistor (30) and the digit line (12) and has a gate (36) connected to a clocked source of a reference potential between a digit line precharge level and the level of one threshold above ground. After the state of a memory cell (16) is read out by a sense amplifier (20), the reference potential is applied to the gate (36) of the third transistor (34) to discharge the gate of the second transistor (30) in the event that the digit line (12) is at a low voltage. If the cell read out on the digit line (12) was at a high potential the gate (32) of the second transistor (30) remains charged so that when a potential exceeding the drain voltage by at least one threshold is applied to the drain of the second transistor (30) it is coupled through to the gate (28) of the first transistor (26) which in turn pulls the digit line potential to the drain supply voltage.
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