公开(公告)号：WO1985003176A1

公开(公告)日：1985-07-18

申请号：PCT/US1984002133

申请日：1984-12-31

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  LEVINE, Steven, N.

IPC: H03L07/00

CPC classification number: H03D13/00 ,  H03K23/662 ,  H03L7/095 ,  H03L7/0993 ,  H04L7/0331

Abstract: An improved multiple frequency digital phase-locked loop circuit (10). The improved digital phase-locked loops utilizes a single circuit (12) to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal (30) with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of the lock detector (22) wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.

Abstract translation: 一种改进的多频数字锁相环电路（10）。 改进的数字锁相环使用单个电路（12）来实现相位和频率调整。 多频数字锁相环通过用导出的可编程时钟信号有选择地组合或减去参考时钟信号（30）来实现相位调整，从而产生复合数字锁相环时钟信号。 多频率通过以可编程可控制的时钟信号确定的速率选择性地从复合时钟信号中增加或减去脉冲来提供频率调节。 改进的多频数字锁相环适合用作附加锁定检测器（22）的音调检测器，其中锁相环可以被编程为多个已知的工作频率。