公开(公告)号：WO1996008762A2

公开(公告)日：1996-03-21

申请号：PCT/IB1995000667

申请日：1995-08-21

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  MIZRAHI-SHALOM, Ori ,  KO, Kung-Ling

IPC: G06F09/30

CPC classification number: G06F9/324 ,  G06F9/30149 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3816

Abstract: A microcontroller or processor architecture that performs word aligned multibyte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with the complete return address which is byte aligned.

Abstract translation: 执行字对齐多字节读取但允许字节对齐指令的微控制器或处理器架构。 跳转目标地址是字对齐的，导致跳转到指令的字对齐获取。 汇编器或编译器将代码加载到指令存储器中，其中分支指令目标地址在字边界上对齐。 从中断返回使用字节对齐的完整返回地址加载程序计数器。