公开(公告)号：WO9708708A3

公开(公告)日：1997-04-03

申请号：PCT/IB9600842

申请日：1996-08-26

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G11C27/02

CPC classification number: G11C27/028

Abstract: A current memory for balanced current inputs comprises two coarse (M1, M11) and two fine (M2, M12) current memory cells each of which comprises a field effect transistor (T1, T11, T2, T12) having a switch (S3, S13, S4, S14) between its gate and source electrodes. Parasitic gate-drain capacitances (C3, C13, C4, C14) are neutralised by capacitors (C31-C34) connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors (C31-C34).

公开(公告)号：WO9708644A3

公开(公告)日：1997-04-10

申请号：PCT/IB9600846

申请日：1996-08-26

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G06G7/186 ,  G06G7/184 ,  G06G7/18

CPC classification number: G06G7/184

Abstract: Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories (3, 4), the second current memory (4) having a plurality of scaled outputs which feed switching arrangements (20, 21). A resistor (R1, R2) is provided in the current memories, the resistance of the resistors being equal to the 'on' resistance of the switching arrangement multiplied by any multiplying factor applied to the output to which the switching arrangement is coupled.

公开(公告)号：WO9708710A2

公开(公告)日：1997-03-06

申请号：PCT/IB9600845

申请日：1996-08-26

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G11C27/02

CPC classification number: G11C27/028

Abstract: A current memory comprises an input (1) which is connected via a switch (S1) which is closed on a phase phi 1 of a clock signal to inputs of a coarse memory cell (CM) and a fine memory cell (FM). The coarse memory cell samples the input current on phase phi 1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory (CM) on phase phi 1b of the clock. A switch (S5) which is closed on phase phi 2 of the clock passes the combined outputs of the coarse (CM) and fine (FM) memories to an output (2). A resistor rs is provided having a resistance equal to the "on" resistance of the output switch (S5). This compensates for the voltage drop across the output switch (S5).

Abstract translation: 当前存储器包括经由开关（S1）连接的输入（1），开关（S1）在时钟信号的相位ph 1上关闭到粗略存储器单元（CM）和精细存储单元（FM）的输入。 粗略存储单元对时钟的相位phi1a上的输入电流进行采样，然后输出电流。 精细存储单元感测时钟的相位phi 1b上的粗略存储器（CM）的输入电流和输出之间的差异。 在时钟的相位phi 2上闭合的开关（S5）将粗略（CM）和精细（FM）存储器的组合输出传递到输出端（2）。 提供电阻rs，其电阻等于输出开关的“导通”电阻（S5）。 这可以补偿输出开关两端的电压降（S5）。

公开(公告)号：WO9708709A3

公开(公告)日：1997-04-03

申请号：PCT/IB9600843

申请日：1996-08-26

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G11C27/02

CPC classification number: G11C27/028

Abstract: A current memory comprises an input (1) which is connected via a switch (S1) which is closed on a phase ζ1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell (M2). The coarse memory cell samples the input current on phase ζ1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory (M1) on phase ζ1b of the clock. A switch (S2) which is closed on phase ζ2 of the clock passes the combined outputs of the coarse (M1) and fine (M2) memories to an output 3. Two further switches (S6, S7) are provided which are closed for a short time (sh1) at the start of phase ζ1b. These serve to discharge the stray capacitance (Cn) at the node (2) to the voltage reference source via terminal 4.

Abstract translation: 当前存储器包括经由在时钟信号的相位ζ1上闭合的开关（S1）连接到粗存储器单元（M1）和精细存储器单元（M2）的输入端的输入端（1）。 粗存储单元在时钟的相位ζ1a上对输入电流进行采样，然后输出电流。 精细存储单元在时钟的相位ζ1b上感测输入电流与粗存储器（M1）的输出之间的差异。 在时钟的相位ζ2上闭合的开关（S2）将粗（M1）和精（M2）存储器的组合输出传送到输出3.提供另外两个开关（S6，S7），其关闭 短时间（sh1）在阶段ζ1b开始。 它们用于通过端子4将节点（2）处的杂散电容（Cn）释放至电压参考源。

公开(公告)号：WO9621905A3

公开(公告)日：1996-09-19

申请号：PCT/IB9600011

申请日：1996-01-08

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G06G7/18

CPC classification number: G06G7/18

Abstract: A switched current differentiator comprises first and second interconnected current memory cells (M1, M2). An input current is applied to terminal (1) and is fed on line (2) to the current memory cells (M1, M2). A first output current is derived from the first current memory cell (M1) via transistor (T3) and a second output current is derived from the second current memory cell (M2) via transistor (T4). The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output (3) via a switch (S3) on odd phases of a clock signal and is fed directly to the output (3) via a switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feedback loop (T5, T6, A3, A4, S5, S6). In a fully differential version of the differentiator the inverters (A1 to A4) may be constructed by the correct interconnection of the differential signals i.e. by crossing over connections.