公开(公告)号：WO2009151670A2

公开(公告)日：2009-12-17

申请号：PCT/US2009/036444

申请日：2009-03-08

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  McALLISTER, Gene H. ,  DABAG, Hayg-Taniel

Inventor： SEO, Dongwon ,  McALLISTER, Gene H. ,  DABAG, Hayg-Taniel

IPC: G06G7/18 ,  H03M1/66 ,  H03M1/00

CPC classification number: H03M1/004 ,  H03M1/066 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

Abstract translation: 根据本发明的至少一个实施例，装置可以包括第一，第二和第三电路。 第一电路接收输入数据并提供基于输入数据而断言的多个第一信号。 第二电路接收多个第一信号并提供用于选择多个电路元件的多个第二信号。 第三电路使用输入数据的分数数据权重生成第二电路的控制，第二电路基于来自第三电路的控制将多个第一信号映射到多个第二信号。

公开(公告)号：WO2018217786A1

公开(公告)日：2018-11-29

申请号：PCT/US2018/033935

申请日：2018-05-22

Applicant: KANDOU LABS, S.A. ,  INVENTION MINE, LLC

Inventor： TAJALLI, Armin

IPC: H04L25/02 ,  H04L25/03 ,  H03K5/1534 ,  G06G7/18 ,  H03M3/04

Abstract: Methods and systems are described for obtaining, at an input stage of a sampler, a continuous-time analog differential voltage, and responsively generating an integrated analog differential voltage by discharging a pair of pre-charged output nodes in an integration period according to the continuous-time analog differential voltage, the integration period initiated by a sampling clock, and providing the integrated analog differential voltage to a plurality of slicing circuits having inputs connected to the pair of output nodes, each slicing circuit of the plurality of slicing circuits generating a respective sliced output signal based on a respective slicing threshold of a set of slicing thresholds.

公开(公告)号：WO2007044191A3

公开(公告)日：2009-04-23

申请号：PCT/US2006036786

申请日：2006-09-21

Applicant: RJS TECHNOLOGY INC ,  DAVIDOVICI SORIN

Inventor： DAVIDOVICI SORIN

IPC: G06G7/18 ,  G06G7/186 ,  H04N5/355

CPC classification number: H04N5/243 ,  G01J1/44 ,  H03M1/64 ,  H04N5/235 ,  H04N5/2351 ,  H04N5/35527 ,  H04N5/378

Abstract: Integrators are electronic components used to condition received analog signals, for example prior to Analog to Digital Conversion. Wide dynamic range, high gain and fine resolution are required of integrators and Analog to Digital Converters in order to limit the effects of noise, including quantization noise. Conventional integrators preceding Analog to Digital Converters are not capable of effectively meeting these requirements. A novel phase domain integrator that can meet effectively these requirements and is superior to conventional integrators for a wide range of applications is disclosed.

Abstract translation: 积分器是用于调节接收的模拟信号的电子元件，例如在模数转换之前。 集成商和模数转换器需要宽动态范围，高增益和精细分辨率，以限制噪声的影响，包括量化噪声。 模数转换器之前的传统集成商不能有效地满足这些要求。 公开了一种新颖的相域积分器，能够有效地满足这些要求，并且在广泛的应用中优于传统的积分器。

公开(公告)号：WO2006065500A3

公开(公告)日：2006-06-22

申请号：PCT/US2005/042845

申请日：2005-11-28

Applicant: L-3 COMMUNICATIONS CORPORATION ,  BRADY, John F., III ,  GALEEMA, Stephen D.

Inventor： BRADY, John F., III ,  GALEEMA, Stephen D.

IPC: G06F7/64 ,  G06G7/18 ,  G06G7/19

Abstract: An integrating capacitor circuit (Figure 1C) for an integrating amplifier and related methods are disclosed that allow for efficient detection of currents or charges, particularly those produced by pixel cells in a detector image array. By placing a capacitor- connected field effect transistor (FET 120B) in parallel with an integration capacitor (120A) and setting its gate voltage to a selected voltage level, the current or charge from the detector depletes the charge on the gate of the FET capacitor (120B) while integrating on the capacitor (120A). In addition, the gate voltage level can be adjusted to modify the current depleting characteristics of the capacitor-connected FET (120B). The resulting operation of this integrating circuitry provides significant resulting advantages for the integrating amplifier.

公开(公告)号：WO2004097713A2

公开(公告)日：2004-11-11

申请号：PCT/DE2004000223

申请日：2004-02-09

Applicant: DEUTSCHE TELEKOM AG ,  HUBER KLAUS

Inventor： HUBER KLAUS

IPC: G06G7/24 ,  G06G7/18

CPC classification number: G06G7/24

Abstract: The invention relates to analog circuit arrangements for generating output signals, the shape of the curve of which corresponds to or approaches an elliptic function at least in some sections thereof. In order to do so, preferably standard analog modules, such as adders, integrators, multipliers, and differential amplifiers, are interconnected so as to reproduce elliptic time functions in a circuitry-related manner.

Abstract translation: 本发明涉及模拟电路，用于产生输出信号，其波形至少部分对应于椭圆函数或近似。 为了这个目的，标准的模拟块，如加法器，积分器，乘法器，和差分放大优选连接在一起，以复制电路的椭圆时间的函数。

公开(公告)号：WO2019022741A1

公开(公告)日：2019-01-31

申请号：PCT/US2017/044133

申请日：2017-07-27

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： HAIRSTON, Allen W.

IPC: G06G7/184 ,  G06F7/64 ,  G06G7/18 ,  G06G7/19

CPC classification number: G06G7/184 ,  G06F7/64

Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

公开(公告)号：WO2015014268A1

公开(公告)日：2015-02-05

申请号：PCT/CN2014/083205

申请日：2014-07-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： CONNELL, Lawrence E. ,  MCCARTHY, Daniel P. ,  CREED, Brian T.

IPC: G06G7/18

CPC classification number: H03K5/15006

Abstract: An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.

Abstract translation: 一种包括分频器的装置，包括：第一锁存器，被配置为接收第一时钟信号和第一时钟信号的补码，并产生第一锁存器第一输出;以及第二锁存器，以触发器配置耦合到第一锁存器， 包括p沟道晶体管的第一输出电路，其中p沟道晶体管的栅极被配置为接收第一时钟信号，以及n沟道晶体管，其中p沟道晶体管的漏极直接连接到 n沟道晶体管的漏极，其中n沟道晶体管的栅极被配置为接收第一锁存器第一输出，其中n沟道晶体管的源被配置为接收第一时钟信号的补码，并且其中 第一输出电路被配置为产生同相参考信号，以及第二输出电路，被配置为产生正交信号。

公开(公告)号：WO98045798A1

公开(公告)日：1998-10-15

申请号：PCT/US1998/006901

申请日：1998-04-06

IPC: G06G7/186 ,  H03M1/12 ,  G06G7/64 ,  G06G7/18 ,  G06G7/19

CPC classification number: G06G7/1865

Abstract: An integrating circuit (7) that includes an op amp (OPA) and an integrating capacitor (12-1) which is decoupled from the output of the op amp (OPA) and precharged to a positive reference voltage before each integration cycle.

Abstract translation: 一种积分电路（7），其包括运算放大器（OPA）和积分电容器（12-1），其与运算放大器（OPA）的输出端分离，并在每个积分周期之前被预充电为正的参考电压。

公开(公告)号：WO9621905A3

公开(公告)日：1996-09-19

申请号：PCT/IB9600011

申请日：1996-01-08

Applicant: PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

Inventor： HUGHES JOHN BARRY ,  MOULDING KENNETH WILLIAM

IPC: G06G7/18

CPC classification number: G06G7/18

Abstract: A switched current differentiator comprises first and second interconnected current memory cells (M1, M2). An input current is applied to terminal (1) and is fed on line (2) to the current memory cells (M1, M2). A first output current is derived from the first current memory cell (M1) via transistor (T3) and a second output current is derived from the second current memory cell (M2) via transistor (T4). The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output (3) via a switch (S3) on odd phases of a clock signal and is fed directly to the output (3) via a switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feedback loop (T5, T6, A3, A4, S5, S6). In a fully differential version of the differentiator the inverters (A1 to A4) may be constructed by the correct interconnection of the differential signals i.e. by crossing over connections.

公开(公告)号：WO2019173768A1

公开(公告)日：2019-09-12

申请号：PCT/US2019/021444

申请日：2019-03-08

Applicant: EAGLE HARBOR TECHNOLOGIES, INC.

Inventor： PRAGER, James, R. ,  ZIEMBA, Timothy, M. ,  MILLER, Kenneth, E. ,  SLOBODOV, Ilia ,  MELNIK, Paul ,  LISTON, Connor ,  MUGGLI, Kevin ,  YEAGER, Taisheng ,  CARSCADDEN, John, G.

IPC: G01N27/00 ,  G01N27/72 ,  G01N27/82 ,  G01N27/90 ,  G06G7/18 ,  G06G7/186

Abstract: Some embodiments of the invention may include an eddy current nondestructive evaluation device. The eddy current nondestructive evaluation device may include a rotating body; a motor coupled with the rotating body such that the motor rotates the rotating body; a permanent magnet coupled with the rotating body; a pickup coil coupled with the rotating body; and an integrator circuit electrically coupled with the pickup coil that integrates a voltage from the pickup coil to produce integrated voltage data.