公开(公告)号：WO2022115108A1

公开(公告)日：2022-06-02

申请号：PCT/US2020/062523

申请日：2020-11-27

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian Craig ,  EL KHATIB, Rami

IPC: G06F7/00 ,  G06F7/72

Abstract: A computer processing system having at least one accelerator operably configured to compute modular multiplication with a modulus of special form and having a systolic carry-save architecture configured to implement Montgomery multiplication and reduction and having multiple processing element types composed of Full Adders and AND gates.

公开(公告)号：WO2022019886A1

公开(公告)日：2022-01-27

申请号：PCT/US2020/042816

申请日：2020-07-20

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian Craig ,  EL KHATIB, Rami

IPC: H04K1/00 ,  H04L9/08 ,  H04L9/28

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

公开(公告)号：WO2021225578A1

公开(公告)日：2021-11-11

申请号：PCT/US2020/031348

申请日：2020-05-04

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian Craig ,  LANGENBERG, Brandon

IPC: G06F7/72 ,  G06F21/60 ,  H04K1/00

Abstract: A computer processing hardware architecture system in a highly secure isogeny based cryptosystem that includes at least one computer processor operably configured to target accelerating operations involved in isogenies on elliptic curves and having a secret key register operably configured to register a secret key, a pseudo-random function, and a secret message buffer, each operably written to by a 2:4 demultiplexer circuit operably configured to receive outside data in regions therein and read by a 4:2 multiplexer circuit.