公开(公告)号：WO2020036598A1

公开(公告)日：2020-02-20

申请号：PCT/US2018/046825

申请日：2018-08-16

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian, Craig ,  LANGENBERG, Brandon

IPC: H03M13/00

Abstract: A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of F p 2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

公开(公告)号：WO2022146437A1

公开(公告)日：2022-07-07

申请号：PCT/US2020/067597

申请日：2020-12-30

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian C. ,  EL KHATIB, Rami ,  LANGENBERG, Brandon

IPC: H04L9/30 ,  H04K1/00

Abstract: A computer processing system for validating isogeny-based cryptography keys having an electronic computing device with an isogeny-based cryptosystem operably configured to validate public keying material including an elliptic curve by simultaneously computing an elliptic curve supersingularity check along with an elliptic curve public point check.

公开(公告)号：WO2021225578A1

公开(公告)日：2021-11-11

申请号：PCT/US2020/031348

申请日：2020-05-04

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： KOZIEL, Brian Craig ,  LANGENBERG, Brandon

IPC: G06F7/72 ,  G06F21/60 ,  H04K1/00

Abstract: A computer processing hardware architecture system in a highly secure isogeny based cryptosystem that includes at least one computer processor operably configured to target accelerating operations involved in isogenies on elliptic curves and having a secret key register operably configured to register a secret key, a pseudo-random function, and a secret message buffer, each operably written to by a 2:4 demultiplexer circuit operably configured to receive outside data in regions therein and read by a 4:2 multiplexer circuit.