公开(公告)号：WO2016137685A3

公开(公告)日：2016-10-27

申请号：PCT/US2016016120

申请日：2016-02-02

Applicant: QUALCOMM INC

Inventor： ATALLAH FRANCOIS IBRAHIM ,  BOWMAN KEITH ALAN ,  HANSQUINE DAVID JOSEPH WINSTON ,  JEONG JIHOON ,  NGUYEN HOAN HUU

IPC: G11C11/412 ,  G11C11/418 ,  H01L27/11

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Abstract translation: 公开了采用P型场效应晶体管（PFET）读取端口的存储器位单元的读辅助电路。 还公开了相关的存储器系统和方法。 已经观察到，随着节点技术尺寸缩小，对于尺寸相似的FET，PFET驱动电流（即，驱动强度）超过N型FET（NFET）驱动电流。 就此而言，在一个方面，期望提供具有PFET读取端口的存储器位单元，与NFET读取端口相反，以增加对存储器位单元的存储器读取时间，并因此提高存储器读取性能。 为了减轻或避免在读取存储器位单元时可能发生的读取干扰状况，为具有PFET读取端口的存储器位单元提供读取辅助电路。

公开(公告)号：WO2016039966A3

公开(公告)日：2016-05-12

申请号：PCT/US2015046512

申请日：2015-08-24

Applicant: QUALCOMM INC

Inventor： BOWMAN KEITH ALAN ,  BRIDGES JEFFREY TODD ,  RAINA SARTHAK ,  KOLLA YESHWANT NAGARAJ ,  JEONG JIHOON ,  ATALLAH FRANCOIS IBRAHIM ,  FLEDERBACH WILLIAM ROBERT ,  FISCHER JEFFREY HERBERT

IPC: H03K5/156 ,  G06F1/10 ,  H03K5/134

CPC classification number: H03K5/13 ,  G06F1/10 ,  H03K5/134 ,  H03K5/156 ,  H03K2005/00019

Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.

Abstract translation: 用于自适应时钟分配系统中的关键路径时间延迟的操作校准的自动校准电路以及相关的方法和系统被公开。 自适应时钟分配系统包括可调长度延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟电路供电的电源中发生电压下降之后时钟电路的时序裕度劣化。 自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降而降低提供给时钟电路的延迟时钟信号的频率，使得时钟电路在电压期间不超过其性能极限 下垂。 在自适应时钟分配系统中提供自动校准电路，以根据时钟电路的操作条件和环境条件来校准操作期间的动态变化监测器。

公开(公告)号：WO2016137683A2

公开(公告)日：2016-09-01

申请号：PCT/US2016016112

申请日：2016-02-02

Applicant: QUALCOMM INC

Inventor： BOWMAN KEITH ALAN ,  ATALLAH FRANCOIS IBRAHIM ,  HANSQUINE DAVID JOSEPH WINSTON ,  JEONG JIHOON ,  NGUYEN HOAN HUU

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C11/40 ,  H03K19/00315 ,  H03K19/094

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

Abstract translation: 提供了采用P型场效应晶体管（PFET）的主要评估电路的动态标签比较电路，用于降低评估时间，从而提高电路性能。 动态标签比较电路可以作为可搜索存储器的一部分使用或提供，例如寄存器文件或内容可寻址存储器（CAM），作为非限制性示例。 动态标签比较电路包括由用作执行比较逻辑功能的逻辑的一个或多个PFET组成的一个或多个PFET主导评估电路。 PFET优势评估电路被配置为接收并比较输入搜索数据到包含在可搜索存储器中的标签（例如，地址或数据），以确定输入搜索数据是否包含在存储器中。 PFET主导评估电路被配置为基于对所接收的输入搜索数据是否包含在可搜索存储器中的评估来控制动态标签比较电路中的动态节点上的电压/值。

公开(公告)号：WO2016137681A3

公开(公告)日：2016-12-15

申请号：PCT/US2016016096

申请日：2016-02-02

Applicant: QUALCOMM INC

Inventor： NGUYEN HOAN HUU ,  ATALLAH FRANCOIS IBRAHIM ,  BOWMAN KEITH ALAN ,  HANSQUINE DAVID JOSEPH WINSTON ,  JEONG JIHOON

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C7/08 ,  G11C11/412 ,  G11C11/418

Abstract: P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells ("bit cells") are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.

Abstract translation: 公开了用于读取PFET通道存储器位单元（“位单元”）的P型场效应晶体管（PFET）读出放大器。 还公开了相关方法和系统。 感测放大器设置在存储器系统中以感测比特单元的位线电压，用于读取存储在位单元中的数据。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过由类型尺寸的FET引起的N型场效应晶体管（NFET）驱动电流。 在这方面，在一方面，在存储器系统中提供基于PFET的读出放大器，以将存储器读取时间增加到位单元，从而提高存储器读取性能。