公开(公告)号：WO2015187482A8

公开(公告)日：2016-01-28

申请号：PCT/US2015033155

申请日：2015-05-29

Applicant: UNIV YALE

Inventor： SUN XIAO ,  MA TSO-PING

IPC: H03K17/06

CPC classification number: H03K19/01714 ,  H03K3/356113 ,  H03K19/094

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract translation: 本公开的示例性实施例涉及自举模块和利用自举模块补偿弱高条件的逻辑电路。 可以使用具有与在逻辑电路中使用的晶体管的通道类型相同的单通道类型的晶体管来实现自举模块，使得可以在解决这种单极电路的弱高问题的同时实现真正的单极电路。

公开(公告)号：WO2018156245A1

公开(公告)日：2018-08-30

申请号：PCT/US2018/012046

申请日：2018-01-02

Applicant: QUALCOMM INCORPORATED

Inventor： KAMAL, Pratyush ,  SAMADI, Kambiz ,  XIE, Jing ,  DU, Yang

IPC: H03K19/09 ,  H01L23/52 ,  H01L27/11 ,  G06F17/50

CPC classification number: H03K19/094 ,  G06F17/505 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11872 ,  H01L2027/11875

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

公开(公告)号：WO2017142482A1

公开(公告)日：2017-08-24

申请号：PCT/SG2017/050070

申请日：2017-02-16

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： CHOI, Pilsoon ,  BOON, Chirn-Chye ,  PEH, Li-Shiuan

IPC: H03K19/20 ,  H01L21/18 ,  H01L21/335 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/085 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/68 ,  H01L29/772 ,  H03K19/0175 ,  H03K19/094

CPC classification number: H01L21/18 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/68 ,  H01L29/772 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/20

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

Abstract translation: 用于高电压系统应用的高压逻辑电路包括由第一半导体材料形成的第一器件层并且包括低电压逻辑电路; 以及第二器件层，其由第二不同半导体材料形成并且包括用于从低压逻辑电路的低压逻辑输入生成高压逻辑输出的附加电路的一个或多个组件; 其中第一和第二器件层一体形成。 而且，一种逻辑电路包括：低电压逻辑输入; 高电源电压输入; 电路接地电压输入; 高电压输出; 由第一半导体材料制成的第一尾部装置; 以及由第二不同半导体材料制成的第二尾部装置; 其中所述第一和第二尾端装置串联耦合在所述高电压输出和所述电路接地电压输入之间; 并且其中第一尾部装置和第二尾部装置的相应的栅极并联耦合到低电压逻辑输入

公开(公告)号：WO2015177982A1

公开(公告)日：2015-11-26

申请号：PCT/JP2015/002378

申请日：2015-05-11

Applicant: ソニー株式会社

Inventor： 鈴木　毅

IPC: H03K19/094 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092

CPC classification number: H03K19/0948 ,  G01R31/2621 ,  H01L22/34 ,  H01L27/092 ,  H03K19/094 ,  H03K19/1737

Abstract: 【課題】ＭＯＳトランジスタのリーク電流を抑制することができる半導体装置及びＭＯＳトランジスタの制御方法を提供すること。 【解決手段】半導体装置は、ＭＯＳトランジスタと、前記ＭＯＳトランジスタがオフのときに、前記ＭＯＳトランジスタの閾値を浅い方向にコントロールするための電圧を、前記ＭＯＳトランジスタの基板に印加するための電圧印加部とを具備する。

Abstract translation: [问题]提供：能够抑制MOS晶体管中的漏电流的半导体器件; 以及用于控制MOS晶体管的方法。 [解决方案]半导体器件配备有MOS晶体管和电压施加单元，其用于在MOS晶体管截止时将用于将MOS晶体管阈值控制到下方的电压施加到MOS晶体管的基板。

公开(公告)号：WO2013018061A1

公开(公告)日：2013-02-07

申请号：PCT/IB2012/053972

申请日：2012-08-02

Applicant: BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY ,  FISH, Alexander ,  KAIZERMAN, Asaf ,  FISHER, Sagi ,  LEVY, Itamar

Inventor： FISH, Alexander ,  KAIZERMAN, Asaf ,  FISHER, Sagi ,  LEVY, Itamar

IPC: H03K19/088 ,  H03K19/02 ,  H03K19/00

CPC classification number: G06F17/5045 ,  G06F9/3869 ,  G06F17/50 ,  G06F17/505 ,  G06F2217/02 ,  H03K19/02 ,  H03K19/094 ,  H03K19/20

Abstract: A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element.

Abstract translation: 用于在静态和动态模式中的任意一种可选择操作的双模逻辑门包括：静态门，其包括至少一个逻辑输入和逻辑输出; 模式选择器，被配置为输出关闭信号以选择静态模式操作并输出动态时钟信号以选择动态模式操作; 以及与模式选择器静态门相关联的开关元件，包括连接到恒定电压的第一输入端，用于从模式选择器输入模式选择信号的第二输入端和连接到静态门极逻辑输出端的输出端。 开关元件通过将适当的信号施加到开关元件来将逻辑门操作从静态切换到动态模式。

公开(公告)号：WO2012052623A1

公开(公告)日：2012-04-26

申请号：PCT/FI2011/050922

申请日：2011-10-20

Applicant: AALTO UNIVERSITY FOUNDATION ,  TURNQUIST, Matthew ,  KOSKINEN, Lauri ,  MÄKIPÄÄ, Jani ,  LAULAINEN, Erkka

Inventor： TURNQUIST, Matthew ,  KOSKINEN, Lauri ,  MÄKIPÄÄ, Jani ,  LAULAINEN, Erkka

IPC: H03K19/017 ,  H03K17/687 ,  H03K19/094

CPC classification number: H03K19/094 ,  H03K19/017 ,  H03K19/09436

Abstract: A field effect transistor current mode differential logic circuit comprising load transistors (M5, M6) for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current mode logic (MCML) operation.

Abstract translation: 一种场效应晶体管电流模式差分逻辑电路，包括用于将每个差分支路电流的电流输出转换为电压输出的负载晶体管（M5，M6），以及用于将每个差分支路的负载晶体管的体积配置为连接到 用于使用亚阈值源耦合逻辑（STSCL）模式中的逻辑电路的负载晶体管，以及用于配置要连接到用于MOS电流模式逻辑的相同晶体管的电压或源极的每个支路负载晶体管的体积的装置（ MCML）操作。

公开(公告)号：WO2017113058A1

公开(公告)日：2017-07-06

申请号：PCT/CN2015/099208

申请日：2015-12-28

Applicant: 京微雅格(北京)科技有限公司

Inventor： 宋惠远

IPC: G06F17/50 ,  H03K19/094

CPC classification number: G06F17/50 ,  H03K19/094

Abstract: 一种基于PLB的FPGA芯片布线方法，该方法包括：分析FPGA芯片的多种布局方式，分别获取每种布局方式中多路复用器的配置规律（S201）；存储所述多种布局方式中的多路复用器的不同配置规律（S202）；在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB（S203）；然后在所述可编程逻辑块PLB层面进行布线（S204）。根据芯片多路复用器布局的结果，进行查找和调用该布局结果所对应存储的多路复用器的配置方式，减少布线器所需处理的基本单元数量和线网数量，进而缩短布线的时间，同时也降低布线算法所占用的内存，提高布线流程的效率。

公开(公告)号：WO2017019064A1

公开(公告)日：2017-02-02

申请号：PCT/US2015/042696

申请日：2015-07-29

Applicant: SCHOBER, Robert, C. ,  SCHOBER, Susan, Marya

Inventor： SCHOBER, Robert, C. ,  SCHOBER, Susan, Marya

IPC: H03K19/094

CPC classification number: H03K19/094 ,  H03K19/018564

Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Abstract translation: 本发明涉及一种新型和本发明的复合器件结构，其能够利用次阈值操作的电荷方法来设计模拟CMOS电路。 特别地，本发明涉及一种基于n型和p型电流场效应晶体管的互补对的固态器件，每一个具有两个控制端口，即低阻抗端口和栅极控制端口，同时 传统的固态设备具有一个控制端口，即门控端口。 这种新颖的固态器件相对于常规器件提供了各种改进。

公开(公告)号：WO2016137683A2

公开(公告)日：2016-09-01

申请号：PCT/US2016016112

申请日：2016-02-02

Applicant: QUALCOMM INC

Inventor： BOWMAN KEITH ALAN ,  ATALLAH FRANCOIS IBRAHIM ,  HANSQUINE DAVID JOSEPH WINSTON ,  JEONG JIHOON ,  NGUYEN HOAN HUU

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C11/40 ,  H03K19/00315 ,  H03K19/094

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

Abstract translation: 提供了采用P型场效应晶体管（PFET）的主要评估电路的动态标签比较电路，用于降低评估时间，从而提高电路性能。 动态标签比较电路可以作为可搜索存储器的一部分使用或提供，例如寄存器文件或内容可寻址存储器（CAM），作为非限制性示例。 动态标签比较电路包括由用作执行比较逻辑功能的逻辑的一个或多个PFET组成的一个或多个PFET主导评估电路。 PFET优势评估电路被配置为接收并比较输入搜索数据到包含在可搜索存储器中的标签（例如，地址或数据），以确定输入搜索数据是否包含在存储器中。 PFET主导评估电路被配置为基于对所接收的输入搜索数据是否包含在可搜索存储器中的评估来控制动态标签比较电路中的动态节点上的电压/值。

公开(公告)号：WO2013164958A1

公开(公告)日：2013-11-07

申请号：PCT/JP2013/061696

申请日：2013-04-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： KUROKAWA, Yoshiyuki

IPC: H03K19/177

CPC classification number: H03K19/0013 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1225 ,  H03K19/094 ,  H03K19/17744

Abstract: Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups.

Abstract translation: 公开了一种可以高速进行动态配置的可编程逻辑器件（PLD）。 PLD包括多个可编程逻辑元件（PLE）和用于选择PLE之间的电连接的开关。 开关包括多个电路组，每个电路组包括第一和第二晶体管。 电路组的第二晶体管彼此并联电连接。 在每个电路组中，基于保持在第二晶体管的栅极和第一晶体管的漏极之间的节点上的配置数据来确定第二晶体管的源极和漏极之间的导电性，其允许选择 通过选择一个电路组，可编程逻辑元件之间的电连接和断开。