公开(公告)号：WO2008101210A3

公开(公告)日：2009-10-22

申请号：PCT/US2008054162

申请日：2008-02-15

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  DORBIE ANGUS M ,  YUN JAY C ,  DU YUN ,  YU CHUN

Inventor： JIAO GUOFANG ,  DORBIE ANGUS M ,  YUN JAY C ,  DU YUN ,  YU CHUN

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T11/40 ,  G09G5/363

Abstract: Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.

Abstract translation: 描述了支持2-D和3-D图形的技术。 图形处理单元（GPU）可以根据3-D图形流水线执行3D图形处理以渲染3-D图像，并且还可以根据2-D图形流水线执行2-D图形处理以呈现2 -D图像。 2-D图形管线的每个阶段可以映射到3-D图形流水线的至少一个阶段。 例如，2-D图形中的裁剪，掩蔽和裁剪阶段可能被映射到3-D图形中的深度测试阶段。 2-D图形中路径内像素的覆盖值可以使用3-D图形中的光栅化和深度测试阶段来确定。 2-D图形中的油漆生成阶段和图像插值阶段可以映射到3-D图形中的片段着色器阶段。 2-D图形中的混合阶段可以映射到3-D图形的混合阶段。

公开(公告)号：WO2008064225A3

公开(公告)日：2008-10-02

申请号：PCT/US2007085241

申请日：2007-11-20

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  DORBIE ANGUS M

Inventor： JIAO GUOFANG ,  DORBIE ANGUS M

IPC: G06T15/30

CPC classification number: G06T15/30 ,  G06T2200/28

Abstract: Scissoring for any number of scissoring regions is performed in a sequential order by drawing one scissoring region at a time on a drawing surface and updating scissor values for pixels within each scissoring region. A scissor value for a pixel may indicate the number of scissoring regions covering the pixel and may be incremented for each scissoring region covering the pixel. A scissor value for a pixel may also be a bitmap, and a bit for a scissoring region may be set to one if the pixel is within the scissoring region. Pixels within a region of interest are passed and rendered, and pixels outside of the region are discarded. This region may be defined by a reference value, which may be set to (a) one for the union of all scissoring regions, for a scissoring UNION operation, or (b) larger than one for the intersection of multiple (e.g., all) scissoring regions, for a scissoring AND operation.

Abstract translation: 通过在绘图表面上一次绘制一个剪刀区域并且更新每个剪刀区域内的像素的剪刀值来按顺序执行任何数量的剪刀区域的剪刀。 像素的剪刀值可以指示覆盖像素的剪切区域的数量，并且可以针对覆盖像素的每个剪切区域递增。 像素的剪刀值也可以是位图，并且如果像素在剪刀区域内，则剪刀区域的位可以被设置为1。 感兴趣区域内的像素被传递并渲染，并且该区域外的像素被丢弃。 该区域可以由参考值定义，该参考值可以被设置为（a）用于所有剪切区域的联合，用于剪切UNION操作，或者（b）用于多个（例如，全部）交点的大于1的参考值， 剪裁区域，用于剪裁和操作。

公开(公告)号：WO2008017058A2

公开(公告)日：2008-02-07

申请号：PCT/US2007075135

申请日：2007-08-02

Applicant: QUALCOMM INC ,  DORBIE ANGUS M ,  JIAO GUOFANG

Inventor： DORBIE ANGUS M ,  JIAO GUOFANG

IPC: G06T11/40 ,  G06T15/00

CPC classification number: G06T11/40

Abstract: The system includes a bounds primitive rasterizer that rasterizes a bounds primitive into a selection of primitive pixels. The selection of primitive pixels bounds a shape to be rendered to a screen. The system also includes a pixel mask generator that generates a pixel mask for the shape. The pixel mask includes mask pixels that each corresponds to one of the primitive pixels. A mask pixel is a covered pixel when the shape covers at least a threshold portion of the mask pixel and is an uncovered pixel when the shape does not cover the mask pixel. The system also includes a pixel screener configured to retain primitive pixels that correspond to covered mask pixels and to discard primitive pixels that correspond to uncovered mask pixels.

Abstract translation: 该系统包括一个边界基元栅格化器，它将边界基元栅格化为原始像素的选择。 原始像素的选择限定了要呈现给屏幕的形状。 该系统还包括为该形状生成像素掩模的像素掩模生成器。 像素掩模包括每个对应于原始像素中的一个的掩模像素。 当形状覆盖掩模像素的至少一个阈值部分时，掩模像素是被覆盖的像素，并且当形状没有覆盖掩模像素时，掩模像素是未覆盖的像素。 该系统还包括像素筛选器，该像素筛选器被配置为保留对应于被覆盖的掩模像素的原始像素并丢弃对应于未覆盖的掩模像素的原始像素。

公开(公告)号：WO2010077612A3

公开(公告)日：2010-10-28

申请号：PCT/US2009067000

申请日：2009-12-07

Applicant: QUALCOMM INC ,  BOURD ALEXEI V ,  JIAO GUOFANG ,  YUN JAY CHUNSUP

Inventor： BOURD ALEXEI V ,  JIAO GUOFANG ,  YUN JAY CHUNSUP

IPC: G06T11/20

CPC classification number: G06T11/203

Abstract: This disclosure describes techniques for removing vertex points during two dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.

Abstract translation: 本发明描述用于在使用三维（3D）图形硬件的二维（2D）图形呈现期间移除顶点的技术。 根据所描述的技术，在使用3D图形硬件的2D图形呈现期间可以移除一个或多个顶点。 例如，这些技术可以通过丢弃在显示坐标空间中具有与先前顶点相同的位置坐标的顶点来移除显示坐标空间中的多余顶点。 可选地或另外地，这些技术可以去除位于直线上的多余顶点。 去除位于一条直线上的冗余顶点或顶点可以更有效地利用GPU的硬件资源，并提高GPU呈现图像以供显示的速度。

公开(公告)号：WO2008128097A3

公开(公告)日：2008-12-24

申请号：PCT/US2008060103

申请日：2008-04-11

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  CHEN LINGJUN FRANK ,  YU CHUN ,  DU YUN

Inventor： JIAO GUOFANG ,  CHEN LINGJUN FRANK ,  YU CHUN ,  DU YUN

IPC: G06F13/10 ,  G06T15/00 ,  G06T15/40 ,  G06T15/50

CPC classification number: G06T15/005 ,  G06T15/40 ,  G06T15/503

Abstract: In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.

Abstract translation: 一般来说，本发明描述用于使用图形处理单元（GPU）中的可编程处理单元来执行图形操作的技术。 如这里所描述的，GPU包括包含可编程图形处理元件（PGPE）的图形管线。 根据这里描述的技术，任意指令集被加载到PGPE中。 随后，PGPE可以执行该组指令以便生成新的像素对象。 像素对象描述可显示的像素。 新像素对象可以表示对第一像素对象执行图形操作的结果。 显示设备可以显示由新像素对象描述的像素。

公开(公告)号：WO2008048940A2

公开(公告)日：2008-04-24

申请号：PCT/US2007081428

申请日：2007-10-15

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  RUTTENBERG BRAIN ,  YU CHUN ,  DU YUN

Inventor： JIAO GUOFANG ,  RUTTENBERG BRAIN ,  YU CHUN ,  DU YUN

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Abstract translation: 本公开描述了使用一个或多个共享算术逻辑单元（ALU）的图形处理单元（GPU）流水线。 为了促进ALU的这种共享，所公开的GPU流水线的阶段可以相对于传统的GPU管线重新排列。 此外，通过重新排列GPU流水线的各个阶段，可以在图像处理中实现效率。 与传统GPU流水线不同，例如，属性梯度建立阶段可以在流水线后面定位，并且属性内插器阶段可以立即跟随属性梯度建立阶段。 这允许通过属性渐变设置和属性内插器阶段共享ALU。 还描述了用于GPU流水线的若干其它技术和特征，其可以提高性能并且可能实现额外的处理效率。

公开(公告)号：WO2010138870A3

公开(公告)日：2012-04-12

申请号：PCT/US2010036661

申请日：2010-05-28

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  DU YUN ,  CHEN LINGJUN ,  YU CHUN

Inventor： JIAO GUOFANG ,  DU YUN ,  CHEN LINGJUN ,  YU CHUN

IPC: G06T15/00

CPC classification number: G06T15/40 ,  G06T1/20 ,  G06T15/005

Abstract: Techniques are described for processing graphics images with a graphics processing unit (GPU) using deferred vertex shading. An example method includes the following: generating, within a processing pipeline of a graphics processing unit (GPU), vertex coordinates for vertices of each primitive within an image geometry, wherein the vertex coordinates comprise a location and a perspective parameter for each one of the vertices, and wherein the image geometry represents a graphics image; identifying, within the processing pipeline of the GPU, visible primitives within the image geometry based upon the vertex coordinates; and, responsive to identifying the visible primitives, generating, within the processing pipeline of the GPU, vertex attributes only for the vertices of the visible primitives in order to determine surface properties of the graphics image.

Abstract translation: 描述了使用延迟顶点着色处理具有图形处理单元（GPU）的图形图像的技术。 示例性方法包括以下：在图形处理单元（GPU）的处理流水线内生成图像几何中每个图元的顶点的顶点坐标，其中顶点坐标包括位置和透视参数 顶点，并且其中图像几何表示图形图像; 在GPU的处理流水线内识别基于顶点坐标的图像几何图形内的可见原始图形; 并且响应于识别可见原语，在GPU的处理流水线内生成仅针对可见图元的顶点的顶点属性，以便确定图形图像的表面特性。

公开(公告)号：WO2009036314A3

公开(公告)日：2009-07-09

申请号：PCT/US2008076227

申请日：2008-09-12

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  DU YUN ,  YU CHUN

Inventor： JIAO GUOFANG ,  DU YUN ,  YU CHUN

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to 'turn off' power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.

Abstract translation: 配置信息用于确定通过图形处理单元的着色器单元绕过片段着色，着色器单元能够执行顶点着色和片段着色。 基于确定，着色器单元执行顶点着色并绕过片段着色。 可以使用除着色器单元之外的处理元件，例如像素混合器，以执行某些片段着色。 在绕过片段着色的情况下，功率被设计为“关闭”未使用组件的电源。 例如，功率可以关闭到多个算术逻辑单元，着色器单元使用减少数量的算术逻辑单元来执行顶点着色。 着色器单元的至少一个寄存器组可以用作FIFO缓冲器，其存储与纹理数据一起使用的像素属性数据，以分割另一个处理元件的着色操作。

公开(公告)号：WO2009049255A2

公开(公告)日：2009-04-16

申请号：PCT/US2008079644

申请日：2008-10-10

Applicant: QUALCOMM INC ,  DU YUN ,  YU CHUN ,  JIAO GUOFANG

Inventor： DU YUN ,  YU CHUN ,  JIAO GUOFANG

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G06T1/20 ,  Y02D10/171 ,  Y02D50/20

Abstract: Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

Abstract translation: 这里公开了与图形处理单元一起使用的功率控制器。 功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。 功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。 功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

公开(公告)号：WO2008019261A2

公开(公告)日：2008-02-14

申请号：PCT/US2007074882

申请日：2007-07-31

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  RUTTENBERG BRIAN ,  YU CHUN ,  DU YUN

Inventor： JIAO GUOFANG ,  RUTTENBERG BRIAN ,  YU CHUN ,  DU YUN

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.

Abstract translation: 描述了使用扩展顶点高速缓存来处理具有图形处理单元（GPU）的计算机化图像的技术。 这些技术包括创建耦合到GPU管线的扩展顶点高速缓存以减少通过GPU管线的数据量。 GPU管线接收图像的图像几何图形，并将图像几何图形内顶点的属性存储在扩展顶点高速缓存中。 GPU流水线仅将标识顶点的顶点坐标和指示扩展顶点高速缓存中的每个顶点的属性的存储位置的顶点高速缓存索引值传递到沿GPU流水线的其他处理阶段。 这里描述的技术将属性梯度的设置推迟到恰好在GPU流水线中的属性内插之前。 在GPU流水线中的属性插值之前，可以从扩展顶点缓存中检索顶点属性以便进行属性梯度设置。