公开(公告)号：WO2023278173A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/033887

申请日：2022-06-16

Applicant: QUALCOMM INCORPORATED

Inventor： SAHU, Rahul ,  GUPTA, Sharad Kumar ,  KIM, Jung Pill ,  JUNG, Chulmin ,  ABRAHAM, Jais

IPC: G11C29/02 ,  G11C29/00 ,  G11C29/24 ,  G11C29/32 ,  G11C29/12 ,  G11C29/46 ,  G11C2029/1204 ,  G11C2029/3202 ,  G11C29/024 ,  G11C29/10 ,  G11C29/781 ,  G11C29/848 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.