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    LOW LEAKAGE CORE POWER LOWERING (CPE) WRITE ASSIST SCHEME
    1.
    发明申请
    LOW LEAKAGE CORE POWER LOWERING (CPE) WRITE ASSIST SCHEME 审中-公开

    公开(公告)号：WO2021231384A1

    公开(公告)日：2021-11-18

    申请号：PCT/US2021/031715

    申请日：2021-05-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： BHASKARAN, Adithya ,  RAJ, Pradeep ,  SAHU, Rahul ,  GUPTA, Sharad Kumar

    IPC: G11C11/419 ,  G11C5/14 ,  G11C11/417 ,  G11C5/147

    Abstract: Memory system configured to perform write assist, the memory system including: a first head switch, a second head switch and a plurality of memory control circuits, each having: a first column selection switch, the first head switch being coupled between a memory supply voltage rail and the first column selection switch, wherein the first column selection switch is coupled between the first head switch and a supply voltage node for a respective column of a memory; a second column selection switch coupled between the supply voltage node and an electric ground; and a core power lowering (CPL) switch. The second head switch is coupled between the memory supply voltage rail and the CPL switches. The first and second head switches are directly coupled between the memory supply voltage rail and respective voltage rail nodes which are common to all memory control circuits in the plurality of memory control circuits.

    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
    3.
    发明申请
    AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT 审中-公开

    公开(公告)号：WO2019070355A1

    公开(公告)日：2019-04-11

    申请号：PCT/US2018/048824

    申请日：2018-08-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： GUPTA, Sharad Kumar ,  RAJ, Pradeep ,  SAHU, Rahul ,  NARASIMHAN, Mukund

    IPC: G11C7/12 ,  G11C11/419

    Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines (BL; BLB) coupled to the memory cell, a multiplexer (404), and a pull-up circuit (418) coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non¬ zero bit line during the write operation and to clamp the non-zero bit line through read pass transistors (rpO, rpbO) of the multiplexer to approximately a power rail voltage (VDD). Thus, the pull-up circuit (418) may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance of a conventional write driver.

    POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT
    5.
    发明申请
    POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT 审中-公开

    公开(公告)号：WO2021222579A1

    公开(公告)日：2021-11-04

    申请号：PCT/US2021/029911

    申请日：2021-04-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAJ, Pradeep ,  SAHU, Rahul ,  GUPTA, Sharad Kumar ,  JUNG, Chulmin

    IPC: G06F1/3287 ,  G06F1/26 ,  H03K19/00

    Abstract: Apparatuses and methods to reduce leakage current are presented. The apparatus includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by a switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

    A NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE
    9.
    发明申请
    A NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE 审中-公开
    多存储体结构的噪声免疫数据路径方案

    公开(公告)号：WO2018075200A1

    公开(公告)日：2018-04-26

    申请号：PCT/US2017/053284

    申请日：2017-09-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： NARASIMHAN, Mukund ,  GUPTA, Sharad Kumar ,  SHANMUGASUNDARAM, Dharaneedharan

    IPC: G11C11/419 ,  G11C7/02

    CPC classification number: G06F13/1689 ,  G11C7/02 ,  G11C7/1087 ,  G11C7/12 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209 ,  G11C2207/2245

    Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.

    Abstract translation: 在本公开的一个方面中，提供了一种装置。 在一个方面，该装置是一种存储装置。 存储装置包括存储器。 存储器包括第一和第二位单元阵列。 存储装置还包括读出放大器。 读出放大器由第一和第二位单元阵列共享。 另外，读出放大器被配置为在读操作期间放大存储在存储器中的数据。 存储器装置还包括写入电路。 写入电路被配置为在写入操作期间将数据写入存储器。 存储装置还包括控制器。 控制器配置为在读操作期间禁用写电路。

    WORDLINE ADJUSTMENT SCHEME
    10.
    发明申请
    WORDLINE ADJUSTMENT SCHEME 审中-公开
    WORDLINE调整计划

    公开(公告)号：WO2017172150A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/019488

    申请日：2017-02-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： SAHU, Rahul ,  GUPTA, Sharad Kumar

    IPC: G11C8/08 ,  G11C11/413 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.

    Abstract translation: 提供了一种用于操作存储器的存储器和方法。 存储器包括具有晶体管的存储器单元和输出耦合到存储器单元的字线的字线驱动器。 字线驱动器调整字线的电压电平以补偿晶体管的参数。 该方法包括断言字线电压以访问具有晶体管的存储器单元并且调整字线电压以补偿晶体管的参数。 提供另一个内存。 存储器包括存储器单元和输出耦合到存储器单元的字线的字线驱动器。 字线驱动器基于字线的反馈来调整字线的电压电平。

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