公开(公告)号：WO2017160480A1

公开(公告)日：2017-09-21

申请号：PCT/US2017/018876

申请日：2017-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： OPORTUS VALENZUELA, Andres, Alejandro ,  ANSARI, Amin ,  SENIOR, Richard ,  GENG, Nieyan ,  JANAKIRAMAN, Anand ,  CHHABRA, Gurvinder, Singh

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0615 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/65

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

Abstract translation: 所公开的方面涉及基于处理器的系统中的压缩存储器行的基于优先级的访问。 在一个方面，基于处理器的系统中的存储器访问设备接收对存储器的读访问请求。 如果读访问请求的优先级较高，则存储器访问设备使用读访问请求的逻辑存储器地址作为物理存储器地址来访问压缩存储器行。 然而，如果读取访问请求的优先级较低，则存储器访问设备将读取访问请求的逻辑存储器地址转换为由较高优先级行压缩留下的存储器空间中的一个或多个物理存储器地址。 以这种方式，通过消除寻找和访问压缩存储器行所需的间接级别来提高较高优先级压缩存储器访问的效率。

公开(公告)号：WO2018208526A1

公开(公告)日：2018-11-15

申请号：PCT/US2018/030184

申请日：2018-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： SENIOR, Richard ,  KOOB, Christopher, Edward ,  CHHABRA, Gurvinder, Singh ,  OPORTUS VALENZUELA, Andres, Alejandro ,  GENG, Nieyan ,  RAGHAVENDRA, Raghuveer ,  PORTER, Christopher ,  JANAKIRAMAN, Anand

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/60

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2 N compressed data regions, corresponding 2 N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2 N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2 N compressed data regions and one of the 2 N sets of free memory lists based on a modulus of the virtual address and 2 N . The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：WO2018147964A1

公开(公告)日：2018-08-16

申请号：PCT/US2018/013296

申请日：2018-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： SENIOR, Richard ,  KOOB, Christopher, Edward ,  CHHABRA, Gurvinder, Singh ,  OPORTUS VALENZUELA, Andres, Alejandro ,  GENG, Nieyan ,  RAGHAVENDRA, Raghuveer ,  PORTER, Christopher ,  JANAKIRAMAN, Anand

IPC: G06F12/02 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/128 ,  G06F12/023 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/70

Abstract: Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems is disclosed. In this regard, a memory system including a compression circuit is provided. The compression circuit includes a compress circuit that is configured to cache free memory lists using free memory list caches comprising a plurality of buffers. When a number of pointers cached within the free memory list cache falls below a low threshold value, an empty buffer of the plurality of buffers is refilled from a system memory. In some aspects, when a number of pointers of the free memory list cache exceeds a high threshold value, a full buffer of the free memory list cache is emptied to the system memory. In this manner, memory access operations for emptying and refilling the free memory list cache may be minimized.

公开(公告)号：WO2018144184A1

公开(公告)日：2018-08-09

申请号：PCT/US2018/012760

申请日：2018-01-08

Applicant: QUALCOMM INCORPORATED

Inventor： KOOB, Christopher, Edward ,  SENIOR, Richard ,  CHHABRA, Gurvinder, Singh ,  OPORTUS VALENZUELA, Andres, Alejandro ,  GENG, Nieyan ,  RAGHAVENDRA, Raghuveer ,  PORTER, Christopher ,  JANAKIRAMAN, Anand

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：WO2014088668A2

公开(公告)日：2014-06-12

申请号：PCT/US2013/059491

申请日：2013-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： WEI, Justin, Y. ,  DAMBRE, Antoine ,  AHN, Christopher ,  CHHABRA, Gurvinder, Singh

IPC: H04L9/08

CPC classification number: H04L9/0816 ,  H04L9/0662 ,  H04L9/0668 ,  H04L2209/12 ,  H04L2209/122

Abstract: Application of a ZUC cryptographic functions in wireless communication includes receiving a data stream at the wireless communication apparatus and applying the ZUC cryptographic function to the data stream. The ZUC cryptographic function includes generating at least one multi-byte pseudo-random number that provides an index to one of a plurality of substitution boxes. Each of the substitution boxes is further based on one or more normative substitution boxes. The ZUC cryptographic function further includes retrieving a value from each of the substitution boxes using each byte of the multi-byte pseudo-random number, assembling the retrieved values into at least one substituted values, and generating at least one key value based on the substituted values, wherein the key value is used in applying the ZUC cryptographic function to the data stream. The method also includes processing the data stream after application of the ZUC cryptographic function.

Abstract translation: ZUC加密功能在无线通信中的应用包括在无线通信装置处接收数据流并将ZUC加密功能应用于数据流。 ZUC加密功能包括生成至少一个多字节伪随机数，其向多个取代框之一提供索引。 每个替代框进一步基于一个或多个规范性替代框。 ZUC加密功能还包括使用多字节伪随机数的每个字节从每个替换盒中检索一个值，将检索到的值组装成至少一个替换值，并且基于取代的值生成至少一个密钥值 值，其中所述键值用于将ZUC加密功能应用于所述数据流。 该方法还包括在应用ZUC加密功能之后处理数据流。

公开(公告)号：WO2014043363A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059483

申请日：2013-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： WEI, Justin, Y. ,  DAMBRE, Antoine ,  AHN, Christopher ,  CHHABRA, Gurvinder, Singh

IPC: H04L12/861 ,  H04L9/26

CPC classification number: H04W12/04 ,  H04L9/0656 ,  H04L9/0668 ,  H04L9/0891 ,  H04L49/90 ,  H04L63/0457 ,  H04L63/062 ,  H04L63/08 ,  H04L63/162 ,  H04L2209/20 ,  H04L2209/80 ,  H04W12/02 ,  Y02D70/122 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/146

Abstract: Enhanced cryptographic techniques are provided which facilitate higher data rates in a wireless communication system. In one aspect, improvements to the ZUC algorithm are disclosed which can reduce the number of logical operations involved key stream generation, reduce computational burden on a mobile device implementing ZUC, and extend battery life. The disclosed techniques include, for instance, receiving, at a wireless communication apparatus, a data stream having data packets for ciphering or deciphering. The wireless apparatus can generate a cipher key for the cryptographic function, determine a starting address of a first data packet in the data stream and shift the cipher key to align with the starting address of the first data packet. Once aligned, the processing apparatus applies the cryptographic function to a first block of the first data packet using the shifted cipher key and manages a remaining portion of the cipher key to handle arbitrarily aligned data across multiple packets.

Abstract translation: 提供了增强的加密技术，其有助于在无线通信系统中更高的数据速率。 在一方面，公开了对ZUC算法的改进，其可以减少涉及密钥流生成的逻辑操作的数量，减少实现ZUC的移动设备的计算负担，并延长电池寿命。 所公开的技术包括例如在无线通信装置处接收具有用于加密或解密的数据分组的数据流。 无线装置可以生成用于加密功能的加密密钥，确定数据流中的第一数据分组的起始地址，并移位密码密钥以与第一数据分组的起始地址一致。 一旦对准，处理装置使用移位密码密钥将加密功能应用于第一数据包的第一块，并管理密码密钥的剩余部分以处理跨多个分组的任意对齐的数据。

公开(公告)号：WO2013158330A2

公开(公告)日：2013-10-24

申请号：PCT/US2013/033002

申请日：2013-03-19

Applicant: QUALCOMM INCORPORATED

Inventor： CHENG, Steven D. ,  CHHABRA, Gurvinder, Singh

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F9/5094 ,  H04W52/029 ,  Y02D10/22 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: Aspects of the disclosure generally relate to methods and apparatus for wireless communication. In an aspect, a method for dynamically processing data on interleaved multithreaded (MT) systems is provided. The method generally includes monitoring loading on one or more active processor threads, determining whether to remove a task or create an additional task based on the monitored loading of the one or more active processor threads and a number of tasks running on one or more of the one or more active processor threads, and if a determination is made to remove a task or create an additional task, distributing the resulting tasks among one or more available processor threads.

Abstract translation: 本公开的方面通常涉及用于无线通信的方法和装置。 在一方面，提供了一种用于动态处理交错多线程（MT）系统上的数据的方法。 该方法通常包括在一个或多个活动处理器线程上监视加载，基于所监视的一个或多个活动处理器线程的负载来确定是否去除任务或创建附加任务，以及在一个或多个活动处理器线程上运行的多个任务 一个或多个活动处理器线程，并且如果确定移除任务或创建附加任务，则在一个或多个可用处理器线程之间分配所生成的任务。