公开(公告)号：WO2015006659A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/046297

申请日：2014-07-11

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA, Anil ,  NAVADA, Sandeep Suresh ,  CHOUDHARY, Niket Kumar ,  MCILVAINE, Michael Scott ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  DOCKSER, Kenneth Alan

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3861

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in- use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and / or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract translation: 本文公开了一种允许无序处理器重新使用正在使用的物理寄存器的方法和装置。 该方法和装置使用诸如重命名映射表（RMT）和物理寄存器文件（PRF）中的令牌和/或其他标识符的标识符来指示是否允许或不允许将指令结果写入物理寄存器。

公开(公告)号：WO2017040087A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/048008

申请日：2016-08-22

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA, Anil ,  SMITH, Rodney Wayne ,  NAVADA, Sandeep Suresh ,  PRIYADARSHI, Shivam ,  CHOUDHARY, Niket Kumar ,  DAMODARAN, Raguram

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30105 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/3867

Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (LI PRF) and a backing physical register file (PRF). A subset of ouptuts of instructions executed in an instruction pipeline of a processor which are deemed to have a high likelihood of use for one or more future instructions are identified. The subset of instruction outputs are stored in the LI PRF, while all instructon outputs are stored in the backing PRF.

Abstract translation: 系统和方法涉及包括1级物理寄存器文件（LI PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。 识别在处理器的指令流水线中执行的被认为对于一个或多个未来指令具有高可用性的指令的子集。 指令输出的子集存储在LI PRF中，而所有的指令输出都存储在后备PRF中。

公开(公告)号：WO2016195848A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/029484

申请日：2016-04-27

Applicant: QUALCOMM INCORPORATED

Inventor： REDDY, Vimal Kodandarama ,  CHOUDHARY, Niket Kumar ,  MCILVAINE, Michael Scott ,  STREETT, Daren Eugene ,  CLANCY, Robert Douglas ,  DIEFFENDERFER, James Norris ,  MORROW, Michael William

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3844

Abstract: Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.

Abstract translation: 用于减轻分支预测中错误路径分支指令的影响的系统和方法包括分支预测写入队列。 分支预测写入队列的第一条目基于获取第一分支指令的顺序与第一分支指令相关联。 在推测性地执行第一分支指令时，在第一条目中写入第一分支指令的正确方向。 在提交第一分支指令之前，如果在正确路径中推测性地执行第一分支指令，则分支预测写入队列被配置为基于第一条目来更新一个或多个分支预测机制。 如果在错误路径中推测性地执行第一分支指令，则可以防止基于第一条目对一个或多个分支预测机制的更新。

公开(公告)号：WO2015142435A1

公开(公告)日：2015-09-24

申请号：PCT/US2015/014541

申请日：2015-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA, Anil ,  WU, Weidan ,  NAVADA, Sandeep Suresh ,  CHOUDHARY, Niket Kumar ,  SMITH, Rodney Wayne

IPC: G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861

Abstract: Physical register scrubbing in computer microprocessors. Most instructions in a computer program produce some output value that is destined for one or more architected registers. These architected destination registers are renamed, in the processor pipeline, to physical registers in order to improve performance by exposing more instruction level parallelism to the processor. In one aspect, a method comprises identifying, in a reorder buffer, a first instruction and a second instruction, without intervening potential pipeline flushers, that write to the same architected destination register, in order to free the physical register corresponding to the older of the two instructions.

Abstract translation: 计算机微处理器中的物理寄存器擦除。 计算机程序中的大多数指令产生一些输出值，用于一个或多个架构化寄存器。 这些架构化的目标寄存器在处理器流水线中被重命名为物理寄存器，以便通过向处理器暴露更多的指令级并行性来提高性能。 在一个方面，一种方法包括在重排序缓冲器中识别第一指令和第二指令，而不间断地写入到同一架构目的寄存器的潜在流水线冲洗器，以便释放对应于较早的 两个说明。