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公开(公告)号：WO2018054035A1
公开(公告)日：2018-03-29
申请号：PCT/CN2017/079533
申请日：2017-04-06
Applicant: 深圳大学
IPC: G06F12/08
CPC classification number: G06F3/0655 , G06F9/30098 , G06F9/3867
Abstract: 一种基于Spark语义的数据重用方法及其系统，其中，所述方法包括：语义信息收集步骤、收集Spark应用运行时的语义信息（S1）；语义维护步骤、维护来自所述语义信息收集步骤所收集到的语义信息（S2）；数据主动缓存步骤、根据所述语义信息和预设的阈值模型缓存未被用户程序显式缓存的数据（S3）；缓存数据迁移步骤、根据所述语义信息和预设的阈值模型将缓存数据在动态随机存取存储器与固定存储器之间迁移（S4）。本方法及系统能减少重复数据计算，提升计算效率，有效避免了对开发人员经验的依赖。
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2.发明申请
公开(公告)号：WO2017117423A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/069275
申请日：2016-12-29
Applicant: INTEL CORPORATION
Inventor： VALENTINE, Robert , CHARNEY, Mark J. , OULD-AHMED-VALL, Elmoustapha , JHA, Ashish
CPC classification number: G06F9/3016 , G06F9/30043 , G06F9/30098 , G06F9/30109 , G06F9/30112
Abstract: Embodiments of systems, apparatuses, and methods for aggregate gather and scatter are disclosed. In some embodiments, a decoder to decode an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and execution circuitry to execute the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate are described.
Abstract translation: 公开了用于聚集收集和散布的系统，设备和方法的实施例。 在一些实施例中，一种用于解码指令的解码器，其中所述指令包括用于存储器地址位置的索引的字段，立即数，以及起始目的地寄存器操作数和附加目的地寄存器的标识符; 以及执行电路，用于执行解码的指令以从存储器位置的索引所指示的位置处的存储器中收集数据元素并将它们存储在由立即数指定的大小的多个目的地寄存器中。
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公开(公告)号：WO2017112498A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/066749
申请日：2016-12-15
Applicant: INTEL CORPORATION
Inventor： OREN, Ben-Kiki , PARDO, Ilan
CPC classification number: G06F11/1076 , G06F9/3001 , G06F9/30098 , G06F9/3016 , G06F11/1012
Abstract: An apparatus and method are described for enforcement of reserved bits. For example, one embodiment of a processor comprises: a memory management unit to store a set of bits including a set of reserved bits to a system memory; reserved bit enforcement logic to generate a pseudo-random pattern in the reserved bits and an error correction code over the pseudo-random pattern prior to storing the reserved bits; the memory management unit to load the reserved bits including the pseudo-random pattern and the error correction code; the reserved bit enforcement logic to use the error correction code to determine whether the reserved bits have been modified by software; and if the reserved bits have been modified, then the processor to generate an error condition and if not modified, then the processor to continue normal execution.
Abstract translation: 描述了用于强制保留比特的装置和方法。 例如，处理器的一个实施例包括：存储器管理单元，用于将包括一组保留比特的一组比特存储到系统存储器; 保留比特实施逻辑，用于在存储保留比特之前，在保留比特中生成伪随机模式，以及在伪随机模式上生成纠错码; 存储器管理单元加载包括伪随机模式和纠错码的保留比特; 保留位执行逻辑，用于使用纠错码来确定保留位是否已被软件修改; 如果保留位已被修改，则处理器产生错误条件，如果没有修改，则处理器继续正常执行。
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公开(公告)号：WO2017107125A1
公开(公告)日：2017-06-29
申请号：PCT/CN2015/098655
申请日：2015-12-24
Applicant: INTEL CORPORATION , JIN, Jun
Inventor： JIN, Jun , OULD-AHMED-VALL, Elmoustapha
IPC: G06F13/16
CPC classification number: G06F9/30043 , G06F9/30 , G06F9/30021 , G06F9/30098 , G06F9/3887
Abstract: Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can generate a first bitmap comprising a plurality of bits, where the plurality of bits includes a first bit that represents a first memory location. The processor core can determine that the value of the first bit is equal to the value of a second bit in the first bitmap. The processor core can determine the location of the second bit in relation to the first bit in the first bitmap. The processor core can generate a second bitmap including a third bit indicating that the first bit is the last bit in the first bitmap with the same value as the second bit.
Abstract translation: 描述了单指令多数据（SIMD）技术。 处理设备可以包括处理器核心和存储器。 处理器核可以生成包括多个比特的第一位图，其中多个比特包括表示第一存储器位置的第一比特。 处理器内核可以确定第一位的值等于第一位图中的第二位的值。 处理器内核可以确定与第一位图中的第一位有关的第二位的位置。 处理器内核可以生成包括第三位的第二位图，该第三位指示第一位是第一位图中的最后一位，具有与第二位相同的值。
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公开(公告)号：WO2017105718A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061964
申请日：2016-11-15
Applicant: INTEL CORPORATION
Inventor： OULD-AHMED-VALL, Elmoustapha
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30098 , G06F9/3016 , G06F9/3885
Abstract: A processor includes a front end to receive an instruction to perform a vector-based bit manipulation, a decoder to decode the instruction, and a source vector register to store multiple data elements. The processor also includes an execution unit to execute the instruction with a first logic to apply a bit manipulation to each of the multiple data elements within the source vector register in parallel. In addition, the processor includes a retirement unit to retire the instruction.
Abstract translation: 处理器包括用于接收执行基于矢量的位操作的指令的前端，用于解码指令的解码器以及用于存储多个数据元素的源矢量寄存器。 该处理器还包括执行单元，用于执行具有第一逻辑的指令，以并行地将位操作应用于源向量寄存器内的多个数据元素中的每一个。 此外，处理器还包括退休单位，以退休指令。
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Patent Agency Ranking
公开(公告)号：WO2017048662A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051424
申请日：2016-09-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： BURGER, Douglas C. , SMITH, Aaron L.
IPC: G06F9/38
CPC classification number: G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. Embodiments of the disclosed technology use read instructions to retrieve a value from a specified register in the register file of the processor architecture and send the value for use by one or more targets (e.g., other instructions in the instruction block). The read instruction may be predicated such that the instruction is only executed when a predicate condition is satisfied. In some examples of the disclosed technology, a compiler for such processors performs an analysis of the source and/or object code being compiled in order to determine whether operation(s) along conditional paths can be executed before or concurrently with determination of a condition on which the conditional operation(s) depend, thus improving processor efficiency.
Abstract translation: 公开了装置和方法，例如基于混合数据流执行模型的计算机处理器。 所公开技术的实施例使用读取指令来从处理器架构的寄存器文件中的指定寄存器检索值，并发送一个或多个目标（例如，指令块中的其他指令）使用的值。 读取指令可以被假定为仅当满足谓词条件时才执行指令。 在所公开的技术的一些示例中，用于这种处理器的编译器对正被编译的源和/或目标代码进行分析，以便确定沿着条件路径的操作是否可以在确定条件之前或同时执行 条件操作取决于哪些，从而提高处理器的效率。
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公开(公告)号：WO2017048660A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051422
申请日：2016-09-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： BURGER, Douglas C. , SMITH, Aaron L.
IPC: G06F12/0806 , G06F9/38
CPC classification number: G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Systems, apparatuses, and methods related to a block-based processor core composition register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include one or more sharable resources and a programmable composition control register. The programmable composition control register can be used to configure which resources of the one or more sharable resources are shared with other processor cores of the plurality of processor cores.
Abstract translation: 公开了与基于块的处理器核心组合寄存器相关的系统，装置和方法。 在所公开的技术的一个示例中，处理器可以包括多个基于块的处理器核，用于执行包括多个指令块的程序。 相应的基于块的处理器核心可以包括一个或多个可共享资源和可编程组合控制寄存器。 可编程组合控制寄存器可用于配置一个或多个可共享资源的哪些资源与多个处理器核的其他处理器核共享。
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公开(公告)号：WO2017048656A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051417
申请日：2016-09-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： BURGER, Douglas C. , SMITH, Aaron L.
IPC: G06F12/0806 , G06F9/38
CPC classification number: G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.
Abstract translation: 公开了用于逻辑处理器的不同系统寄存器。 在所公开的技术的一个示例中，处理器包括用于执行包括多个指令块的程序的多个基于块的物理处理器核。 处理器还包括线程调度器，其被配置为调度用于执行的程序的线程，线程使用一个或多个指令块。 处理器还包括至少一个系统寄存器。 所述至少一个系统寄存器存储指示多个物理处理器核的数量和布置的数据，以形成逻辑处理器。 逻辑处理器执行调度的线程。 逻辑处理器被配置为在连续指令窗口中执行线程。
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公开(公告)号：WO2017048652A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051413
申请日：2016-09-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： BURGER, Douglas C. , SMITH, Aaron L.
CPC classification number: G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Apparatus and methods are disclosed for dynamic nullification of memory access instructions, such as memory store instructions. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores. One of the cores can include an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block. The core can also include a hardware structure storing data for at least one predicate instruction in the instruction block, the data identifying whether one or more of the memory store instructions will issue if a condition of the predicate instruction is satisfied. The core may further include a control unit configured to control issuing of the memory access instructions to the execution unit based at least in a part on the hardware structure data.
Abstract translation: 公开了用于存储器访问指令的动态无效的装置和方法，诸如存储器存储指令。 在所公开技术的一些示例中，装置可以包括存储器和一个或多个基于块的处理器核。 核心之一可以包括被配置为执行存储器访问指令的执行单元，该存储器访问指令包括包含在指令块中的多个存储器加载和/或存储器存储指令。 核心还可以包括存储指令块中的至少一个谓词指令的数据的硬件结构，如果满足谓词指令的条件，则识别存储器存储指令中的一个或多个是否将发出的数据。 核心可以进一步包括控制单元，其被配置为至少部分地基于硬件结构数据来控制向执行单元发出存储器访问指令。
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公开(公告)号：WO2017048651A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051412
申请日：2016-09-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： BURGER, Douglas C. , SMITH, Aaron L.
IPC: G06F12/0806 , G06F9/38
CPC classification number: G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. In particular embodiments, a processor core in a block-based processor comprises: one or more functional units configured to perform functions using one or more operands; an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window including one or more operand buffers for an individual instruction configured to store operand values; a control unit configured to execute the instructions in the instruction window and control operation of the one or more functional units; and a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.
Abstract translation: 公开了装置和方法，例如基于混合数据流执行模型的计算机处理器。 在特定实施例中，基于块的处理器中的处理器核心包括：被配置为使用一个或多个操作数执行功能的一个或多个功能单元; 指令窗口，包括被配置为存储由处理器核心执行的单独指令的缓冲器，所述指令窗口包括用于存储操作数值的单独指令的一个或多个操作数缓冲器; 控制单元，被配置为执行所述指令窗口中的指令并控制所述一个或多个功能单元的操作; 以及广播值存储器，包括专用于存储广播值的多个缓冲器，广播值存储器的每个缓冲器与多个可用广播信道中的相应广播信道相关联。
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