公开(公告)号：WO2017052966A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048628

申请日：2016-08-25

Applicant: QUALCOMM INCORPORATED

Inventor： PRIYADARSHI, Shivam ,  KRISHNA, Anil ,  DAMODARAN, Raguram ,  BRIDGES, Jeffrey Todd ,  SPEIER, Thomas Philip ,  SMITH, Rodney Wayne ,  BOWMAN, Keith Alan ,  HANSQUINE, David Joseph Winston

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3855 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

Abstract translation: 响应于由于高速缓存未命中而导致的调度停顿，处理器的时钟频率被减小。 在一个实施例中，如果加载指令是最早的加载指令，并且其中存在分派失速的连续处理器周期的数量超过阈值，则针对导致最后一级高速缓存未命中的加载指令减小处理器时钟频率， 并且条件是自上一级高速缓存未命中以来的处理器周期总数不超过某个指定数量。

公开(公告)号：WO2016048749A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/050422

申请日：2015-09-16

Applicant: QUALCOMM INCORPORATED

Inventor： ATALLAH, Francois Ibrahim ,  HANSQUINE, David Joseph Winston ,  TAX, Richard Duane ,  TAYLOR, Robert Simpson

IPC: H03K19/00 ,  G06F1/32

CPC classification number: G06F1/10 ,  G06F1/32 ,  G06F1/3237 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0019 ,  Y02D10/128

Abstract: Systems and methods are directed to a configurable last level driver (202) coupled to a inductor-capacitor (LC) tank (204) or resonant clock, for improving energy efficiency of the resonant clock. In a warm up stage, the last level clock driver can be enabled to store energy in the LC tank, and in a gating stage, the last level clock driver can be fully or partially disabled such that energy stored in the LC tank can be recirculated into a clock distribution network. In a refreshing stage, the last level clock driver can be enabled to replenish the energy lost by the LC tank in the recirculation of energy into the clock distribution network during the gating stage. Programmable counters (222, 226, 230) can be used to control durations (224, 228, 232) of the warm up, gating, and refreshing stages.

Abstract translation: 系统和方法涉及耦合到电感器 - 电容器（LC）箱（204）或谐振时钟的可配置的最后级别驱动器（202），用于提高谐振时钟的能量效率。 在预热阶段，最后一级时钟驱动器可以使能在LC箱中存储能量，并且在选通阶段，最后一级时钟驱动器可以被完全或部分禁用，使得储存在LC箱中的能量可以再循环 进入时钟分配网络。 在更新阶段，可以启用最后一级时钟驱动器，以便在门控阶段期间将能量损失的能量补充到能量进入时钟分配网络中。 可编程计数器（222,226,230）可用于控制预热，选通和刷新阶段的持续时间（224,228,232）。