公开(公告)号：WO2023048977A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/043218

申请日：2022-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： BOWMAN, Keith Alan ,  YINGLING, Daniel ,  PAL, Dipti Ranjan

IPC: G04F10/00 ,  G06F1/10 ,  H03K5/14

Abstract: A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.

公开(公告)号：WO2018125547A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/065558

申请日：2017-12-11

Applicant: QUALCOMM INCORPORATED

Inventor： HO, Lam ,  BOWMAN, Keith Alan ,  TOOSIZADEH, Navid ,  HU, Shih-Hsin Jason ,  KAKOEE, Mohammad Reza ,  KANNAN, Saravana Krishnan

IPC: G06F1/30 ,  G06F1/10

Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

公开(公告)号：WO2023048980A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/043223

申请日：2022-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： BOWMAN, Keith Alan ,  YINGLING, Daniel ,  PAL, Dipti Ranjan

IPC: H03K5/156

Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

公开(公告)号：WO2022245445A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/024260

申请日：2022-04-11

Applicant: QUALCOMM INCORPORATED

Inventor： DIBBAD, Vijayakumar Ashok ,  RANGARAJAN, Bharat Kumar ,  PAL, Dipti Ranjan ,  BOWMAN, Keith Alan ,  SEVERSON, Matthew ,  LEE, Gordon

IPC: G06F1/30 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234

Abstract: In controlling power in a portable computing device ("PCD"), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

公开(公告)号：WO2017222620A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/026590

申请日：2017-04-07

Applicant: QUALCOMM INCORPORATED

Inventor： JAIN, Palkesh ,  BOWMAN, Keith Alan ,  BANSAL, Virendra

IPC: H03K5/135 ,  H03K3/03 ,  H03L7/08 ,  H03K5/00

Abstract: An adaptive clock distribution (ACD) system (100) with a voltage tracking clock generator (VTCG) (108) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit (104), to generate a TLD clock by adding a preselected delay to a root clock (102), and a voltage droop detector (106) for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock (109), wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector (110) selects the VTCG clock (109) as an ACD clock (111) to be provided to an electronic circuit (120) during the voltage droop and the TLD clock (105) as the ACD clock (111) when there is no voltage droop detected.

Abstract translation: 公开了具有电压跟踪时钟发生器（VTCG）（108）的自适应时钟分配（ACD）系统（100）。 ACD系统包括可调长度延迟（TLD）电路（104），用于通过将预选延迟添加到根时钟（102）来生成TLD时钟，以及电压下降检测器（106），用于检测电压下降 电源电压。 VTCG被配置为产生VTCG时钟（109），其中VTCG时钟的频率被微调到两个或更多个值中的一个以对应于电压下降期间的电源电压的大小。 时钟选择器（110）在电压降落期间和TLD时钟（105）期间选择VTCG时钟（109）作为要提供给电子电路（120）的ACD时钟（111）作为ACD时钟（111） 没有检测到电压跌落。

公开(公告)号：WO2022115192A1

公开(公告)日：2022-06-02

申请号：PCT/US2021/056623

申请日：2021-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： PAL, Dipti Ranjan ,  PANT, Harshat ,  ROY, Abinash ,  HU, Shih-Hsin Jason ,  BOWMAN, Keith Alan

IPC: G05F1/46 ,  G05F1/59 ,  G06F1/26

Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

公开(公告)号：WO2017184396A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/027121

申请日：2017-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： JAIN, Palkesh ,  BANSAL, Virendra ,  MEHROTRA, Manoj ,  BOWMAN, Keith Alan

IPC: G06F1/08 ,  G06F1/30

Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

Abstract translation: 本公开针对减轻电压下降。 一个方面包括通过耦合到多路复用器的时钟模块将第一时钟信号输出到多路复用器，第一时钟信号由时钟模块的时钟延迟元件产生，由时钟模块从第一时钟模块接收第二时钟信号 其中所述PLL向耦合到所述PLL和所述多路复用器的处理器输出第三时钟信号，通过所述多路复用器选择所述第一时钟信号以基于检测到所述第一时钟信号中的下垂电压 电源，并且所述多路复用器基于检测到所述电源上的所述电压下降已经过去而选择所述第三时钟信号输出到所述处理器，其中所述时钟模块和所述处理器耦合到所述电源。

公开(公告)号：WO2017052966A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048628

申请日：2016-08-25

Applicant: QUALCOMM INCORPORATED

Inventor： PRIYADARSHI, Shivam ,  KRISHNA, Anil ,  DAMODARAN, Raguram ,  BRIDGES, Jeffrey Todd ,  SPEIER, Thomas Philip ,  SMITH, Rodney Wayne ,  BOWMAN, Keith Alan ,  HANSQUINE, David Joseph Winston

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3855 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

Abstract translation: 响应于由于高速缓存未命中而导致的调度停顿，处理器的时钟频率被减小。 在一个实施例中，如果加载指令是最早的加载指令，并且其中存在分派失速的连续处理器周期的数量超过阈值，则针对导致最后一级高速缓存未命中的加载指令减小处理器时钟频率， 并且条件是自上一级高速缓存未命中以来的处理器周期总数不超过某个指定数量。

公开(公告)号：WO2016048455A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/043602

申请日：2015-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： ATALLAH, Francois Ibrahim ,  JEONG, Jihoon ,  BOWMAN, Keith Alan ,  KULKARNI, Amey Sudhir ,  MARTZLOFF, Jason Philip ,  PUCKETT, Joshua Lance

IPC: G11C11/419

CPC classification number: G11C7/12 ,  G11C5/06 ,  G11C5/147 ,  G11C7/22 ,  G11C11/419 ,  G11C2207/007

Abstract: A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

Abstract translation: 根据本公开的一些示例的寄存器文件电路可以包括存储器单元，标头晶体管电路和驱动器电路。 标头晶体管电路可以包括与存储单元的PFET串联的一个或多个PFET头，用于被写入的行的PFET头的栅极被来自驱动器电路的脉冲写入信号控制。 在本公开的一些示例中，标题晶体管电路可以包括插入在虚拟vdd和地之间的NFET下拉以放电虚拟vdd节点，从而在写入操作期间减少争用并且与PFET头并联的钳位NFET 将虚拟vdd节点钳位到略低于存储单元中的上拉PFET的阈值电压，以确保上拉PFET几乎不会关闭，并防止虚拟vdd节点一直向地面放电。

公开(公告)号：WO2023048978A2

公开(公告)日：2023-03-30

申请号：PCT/US2022/043221

申请日：2022-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： BOWMAN, Keith Alan ,  YINGLING, Daniel ,  PAL, Dipti Ranjan

IPC: H03K5/156 ,  H03K5/05 ,  H03K5/00 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133

Abstract: Aspects of the present disclosure relate to a duty-cycle adjuster (1220) including a first inverter (1235), a first multiplexer (1240), a high-phase extender (1250), a second inverter (1265), and a second multiplexer (1270). The first multiplexer (1240) has a first input (1242), a second input (1244), a select input (1246), and an output (1248). The first input (1242) of the first multiplexer (1240) is coupled to the signal input (1222) of the duty-cycle adjuster (1220), and the select input (1246) of the first multiplexer (1240) is coupled to the first control input (1226). The first inverter (1235) is coupled between the signal input (1222) of the duty-cycle adjuster (1220) and the second input (1244) of the first multiplexer (1240).