公开(公告)号：WO2014113295A1

公开(公告)日：2014-07-24

申请号：PCT/US2014/011138

申请日：2014-01-10

Applicant: QUALCOMM INCORPORATED

Inventor： TERZIOGLU, Esin ,  UVIEGHARA, Gregory Ameriada ,  YOON, Sei Seung ,  GANESAN, Balachander ,  KOTA, Anil Chowdary

IPC: H03K19/003 ,  G11C17/18 ,  H03K17/081

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止双模式PMOS晶体管的电压损坏，尽管其尺寸相对较小并具有较薄的栅极氧化物厚度。

公开(公告)号：WO2022015431A1

公开(公告)日：2022-01-20

申请号：PCT/US2021/036367

申请日：2021-06-08

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  SRIKANTH, Anne

IPC: G11C29/00 ,  G11C17/14 ,  G11C17/18 ,  G11C5/00 ,  G11C29/52

Abstract: The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.

公开(公告)号：WO2021178590A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/020745

申请日：2021-03-03

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  KIM, Keejong

IPC: G11C17/18 ,  G11C7/22 ,  G11C16/34 ,  G11C17/14 ,  G11C17/16 ,  G11C29/02

Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

公开(公告)号：WO2023048961A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/042961

申请日：2022-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  SHETH, Dhvani ,  JUNG, Chulmin

IPC: G11C7/22 ,  G11C11/417 ,  G11C7/08 ,  G11C7/06 ,  G11C11/419 ,  G11C7/12

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：WO2023027857A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/038534

申请日：2022-07-27

Applicant: QUALCOMM INCORPORATED

Inventor： PALLERLA, Arun Babu ,  KOTA, Anil Chowdary ,  LEE, Hochul

IPC: G11C7/06 ,  G11C11/419

Abstract: A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

公开(公告)号：WO2022086641A1

公开(公告)日：2022-04-28

申请号：PCT/US2021/049894

申请日：2021-09-10

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  SRIKANTH, Anne

IPC: G11C17/16 ,  G11C17/18 ,  G11C17/06

Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.

公开(公告)号：WO2023064151A1

公开(公告)日：2023-04-20

申请号：PCT/US2022/045954

申请日：2022-10-06

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  SHETH, Dhvani

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/12

Abstract: A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

公开(公告)号：WO2022098493A1

公开(公告)日：2022-05-12

申请号：PCT/US2021/055342

申请日：2021-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： SHETH, Dhvani ,  KOTA, Anil Chowdary ,  LEE, Hochul ,  JUNG, Chulmin ,  LIANG, Bin

IPC: G11C8/08 ,  G11C8/10

Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.

公开(公告)号：WO2021247176A1

公开(公告)日：2021-12-09

申请号：PCT/US2021/030235

申请日：2021-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： KOTA, Anil Chowdary ,  LEE, Hochul

IPC: G11C7/14 ,  G11C7/06 ,  G11C7/24 ,  G11C29/00 ,  G11C17/16 ,  G11C29/785 ,  G11C29/846 ,  G11C7/062 ,  G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/18

Abstract: A memory device with built-in flexible redundancy is provided according to various aspects. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).