公开(公告)号：WO2016022273A1

公开(公告)日：2016-02-11

申请号：PCT/US2015/041010

申请日：2015-07-17

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Shengyuan ,  SHI, Chunlei ,  NGUYEN, Loc

IPC: H02M1/34

CPC classification number: H02M1/00 ,  H02M1/34 ,  H02M3/158 ,  H02M2001/0003 ,  H02M2001/344

Abstract: The present disclosure includes programmable snubber circuits and methods. In one embodiment, a circuit is configured between first and second power supply terminals. A programmable snubber circuit may be configured between the first and second power supplies to reduce ringing on the power supplies. In one embodiment, the circuit is a switching regulator and the power supply terminals are internal power supply terminals. The snubber circuit may be programmed to reduce ringing caused by switching currents through parasitic inductances in a package.

Abstract translation: 本公开包括可编程缓冲电路和方法。 在一个实施例中，电路被配置在第一和第二电源端子之间。 可编程缓冲电路可以配置在第一和第二电源之间，以减少电源上的振铃。 在一个实施例中，电路是开关调节器，电源端子是内部电源端子。 缓冲电路可以被编程为减少由开关电流通过封装中的寄生电感引起的振铃。

公开(公告)号：WO2016022271A1

公开(公告)日：2016-02-11

申请号：PCT/US2015/041005

申请日：2015-07-17

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Shengyuan ,  MIREA, Iulian

IPC: H03K5/24 ,  H03K19/017 ,  H03K19/0185

CPC classification number: H03K19/0185 ,  H03K3/35613 ,  H03K5/2481 ,  H03K19/01721 ,  H03K19/018514

Abstract: In one embodiment, a method for increasing speed of a differential input pair (102), The method comprises applying a first boost current (M19 on) to a first input of the differential input pair during a transition of a first signal applied to the first input (INP); storing (C0) the first boost current; ending (M19 off) the application of the first boost current (V across C0) in response to the stored first boost current exceeding a first threshold (Vgs of M19); applying a second boost current (M20 on) to a second input of the differential input pair during a transition of a second signal applied to the second input (INN); storing (C1) the second boost current; and ending the application of the second boost current (M20 off) in response to the stored second boost current (V across C1) exceeding a second threshold (Vgs of M20).

Abstract translation: 在一个实施例中，一种用于增加差分输入对（102）的速度的方法。该方法包括：在施加到第一个信号的第一信号的转变期间，向差分输入对的第一输入端施加第一升压电流（M19 on） 输入（INP）; 存储（C0）第一升压电流; 响应于存储的第一升压电流超过第一阈值（Mgs的Vgs），结束（M19关闭）应用第一升压电流（跨过C0的V）; 在施加到第二输入（INN）的第二信号的转变期间，将第二升压电流（M20 on）施加到差分输入对的第二输入端; 存储（C1）第二升压电流; 响应于超过第二阈值（M20的Vgs）的所存储的第二升压电流（跨过C1的V），结束施加第二升压电流（M20关闭）。

公开(公告)号：WO2016018645A1

公开(公告)日：2016-02-04

申请号：PCT/US2015/040984

申请日：2015-07-17

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Shengyuan

IPC: H03K3/356 ,  H03K19/0185

CPC classification number: H03K19/017545 ,  H03K3/356104 ,  H03K19/0005 ,  H03K19/018528

Abstract: In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric.

Abstract translation: 在一个实施例中，电路包括相位插值器，其将单端输入转换成第一电压域内的一对对称差分信号。 电路还包括比较器，其将对称差分信号转换成第二不同电压域中的单端输出。 在一个实施例中，比较器的单端输出被配置为耦合以驱动开关调节器中的开关驱动器。 在一个实施例中，内插器包括串联连接的第一反相器，第二反相器和第三反相器。 内插器还包括串联连接的第一电阻器和第二电阻器。 第二个反相器提供第一个输出信号。 第一个反相器和第三个反相器的输出通过串联电阻连接。 电阻之间的节点提供第二个输出信号。 第一和第二输出信号是反相和对称的。