公开(公告)号：WO2004006460A3

公开(公告)日：2004-01-15

申请号：PCT/US2003/021595

申请日：2003-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRAHMANYA, Parvathanathan ,  LIN, Jeremy, H.

IPC: H04B1/707

Abstract: Techniques for inner/outer loop tracking that is stable and provides desirable loop convergence characteristics are disclosed. In one aspect, the contribution from any one inner loop to the tracking function of the outer loop (260) is limited, to prohibit any one received signal component from dominating the outer loop. In another aspect, the rate of outer loop tracking variation is controlled to provide inner and outer loop stability. Various other aspects are also presented. These aspects have the benefit of providing stable inner and outer loop control, as well as efficient convergence and tracking by the various loops, resulting in reduced frequency error and improved communication performance.

公开(公告)号：WO2009120479A2

公开(公告)日：2009-10-01

申请号：PCT/US2009/036437

申请日：2009-03-07

Applicant: QUALCOMM INCORPORATED ,  CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  GURSKI, Remi ,  YEN, Kevin, W.

Inventor： CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  GURSKI, Remi ,  YEN, Kevin, W.

IPC: G06F15/78 ,  H04M1/725 ,  G06F9/48

CPC classification number: G06F9/3879 ,  G06F15/7814

Abstract: A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract translation: 灵活和可重构的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合的存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路任务管理器从其任务列表中读取任务指令，并根据指令控制其相关的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

公开(公告)号：WO2009123878A1

公开(公告)日：2009-10-08

申请号：PCT/US2009/037994

申请日：2009-03-23

Applicant: QUALCOMM INCORPORATED ,  SAMPATH, Hemanth ,  LIN, Jeremy, H. ,  KANDUKURI NARAYANA, Sunil Kumar ,  VERMANI, Sameer

Inventor： SAMPATH, Hemanth ,  LIN, Jeremy, H. ,  KANDUKURI NARAYANA, Sunil Kumar ,  VERMANI, Sameer

IPC: H04L27/26 ,  H04J3/06

CPC classification number: H04L27/2607 ,  H04L27/2655

Abstract: A method for adjusting timing in a Frequency Division Multiplexing (FDM) system, including receiving a request to perform a timing correction, generating a time domain FDM symbol, and controlling the timing correction in the time domain FDM symbol by at least one of adjusting a length of a cyclic prefix, overlapping a portion of adjacent FDM symbols, adjusting a symbol windowing length, or utilizing a return link (RL) silence interval.

Abstract translation: 一种用于在频分复用（FDM）系统中调整定时的方法，包括接收执行定时校正的请求，产生时域FDM符号，以及通过以下步骤中的至少一个来控​​制时域FDM符号中的定时校正： 循环前缀的长度，与相邻FDM符号的一部分重叠，调整符号加窗长度，或利用返回链路（RL）静默间隔。

公开(公告)号：WO2009120724A2

公开(公告)日：2009-10-01

申请号：PCT/US2009/038146

申请日：2009-03-24

Applicant: QUALCOMM INCORPORATED ,  SAMPATH, Hemanth ,  AGRAWAL, Avneesh ,  LIN, Jeremy, H.

Inventor： SAMPATH, Hemanth ,  AGRAWAL, Avneesh ,  LIN, Jeremy, H.

IPC: H04L25/06 ,  H03M13/45

CPC classification number: H03M13/45 ,  H03M13/6588 ,  H04L1/0046 ,  H04L1/1819 ,  H04L1/1822 ,  H04L1/1835 ,  H04L1/1845 ,  H04L5/0007 ,  H04L25/067

Abstract: A system involves a transmitting device (for example, a first wireless communication device) and a receiving device (for example, a second wireless communication device). In the receiving device, LLR (Log-Likelihood Ratio) values are stored into an LLR buffer. LLR bit width is adjusted as a function of packet size of an incoming transmission to reduce the LLR buffer size required and/or to prevent LLR buffer capacity from being exceeded. The receiver may use a higher performance demodulator in order to maintain performance despite smaller LLR bit width. In the transmitting device, encoder code rate is adjusted as a function of receiver LLR buffer capacity and packet size of the outgoing transmission such that receiver LLR buffer capacity is not exceeded. Any combination of receiver LLR bit width adjustment, demodulator selection, and encoder code rate adjustment can be practiced to reduce LLR buffer size required while maintaining performance.

Abstract translation: 系统涉及发送设备（例如，第一无线通信设备）和接收设备（例如，第二无线通信设备）。 在接收设备中，将LLR（对数似然比）值存储到LLR缓冲器中。 根据输入传输的分组大小调整LLR比特宽度，以减少所需的LLR缓冲区大小和/或防止超出LLR缓冲区容量。 接收机可以使用更高性能的解调器，以便尽管较小的LLR位宽度来保持性能。 在发送设备中，根据接收机LLR缓冲器容量和输出传输的分组大小来调节编码器码率，使得接收机LLR缓冲器容量不被超过。 可以实现接收机LLR位宽度调整，解调器选择和编码器码率调整的任何组合，以在保持性能的同时减少所需的LLR缓冲区大小。

公开(公告)号：WO2009120640A2

公开(公告)日：2009-10-01

申请号：PCT/US2009/037989

申请日：2009-03-23

Applicant: QUALCOMM INCORPORATED ,  SAMPATH, Hemanth ,  ZHANG, Xin ,  LIN, Jeremy, H. ,  SHARMA, Nistha ,  PALANKI, Ravi ,  KANDUKURI NARAYANA, Sunil Kumar

Inventor： SAMPATH, Hemanth ,  ZHANG, Xin ,  LIN, Jeremy, H. ,  SHARMA, Nistha ,  PALANKI, Ravi ,  KANDUKURI NARAYANA, Sunil Kumar

IPC: G06F17/14

CPC classification number: G06F17/142 ,  H04L5/0007 ,  H04L5/0023 ,  H04L5/0053 ,  H04L27/265

Abstract: In embodiments, a wireless receiver employs a hardware-based Fast Fourier Transform (FFT) engine controlled by firmware. The FFT engine executes tasks stored in a task list. Each task is associated with a different portion of a signal, for example, one or more Orthogonal Frequency Division Modulated (OFDM) symbols. Each task may include configuration information for the FFT engine for configuring the engine to process the associated portion of the signal, a pointer to the portion to be processed, and another pointer to the memory for storing the output. The task list may be firmware controlled. Division of the FFT into a configurable hardware part driven by firmware to read and execute the tasks in the task list may speed up the FFT process and make it more flexible. A hardware beacon sorter may be coupled to the FFT engine to sort the sub-carriers according to their energies.

Abstract translation: 在实施例中，无线接收机采用由固件控制的基于硬件的快速傅立叶变换（FFT）引擎。 FFT引擎执行任务列表中存储的任务。 每个任务与信号的不同部分相关联，例如一个或多个正交频分调制（OFDM）符号。 每个任务可以包括用于配置引擎以处理信号的相关部分的引擎的FFT引擎的配置信息，到要处理的部分的指针，以及用于存储输出的另一个指向存储器的指针。 任务列表可以是固件控制的。 将FFT分解为由固件驱动的可配置硬件部分，以读取和执行任务列表中的任务，可加速FFT过程并使其更加灵活。 硬件信标分类器可以耦合到FFT引擎，以根据它们的能量对子载波进行分类。

公开(公告)号：WO2009120480A1

公开(公告)日：2009-10-01

申请号：PCT/US2009/036438

申请日：2009-03-07

Applicant: QUALCOMM INCORPORATED ,  CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  ROSTAMPISHEH, Ali ,  CHALLA, Raghu ,  SAMPATH, Hemanth ,  WU, Megan ,  ZANOTELLI, Joseph ,  NATH, Mrinal

Inventor： CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  ROSTAMPISHEH, Ali ,  CHALLA, Raghu ,  SAMPATH, Hemanth ,  WU, Megan ,  ZANOTELLI, Joseph ,  NATH, Mrinal

IPC: G06F15/78 ,  H04M1/725

CPC classification number: G06F15/7842

Abstract: A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract translation: 灵活和可重构的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合的存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路任务管理器从其任务列表中读取任务指令，并根据指令控制其相关的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

公开(公告)号：WO2009120473A1

公开(公告)日：2009-10-01

申请号：PCT/US2009/036248

申请日：2009-03-05

Applicant: QUALCOMM INCORPORATED ,  CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  GURSKI, Remi

Inventor： CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  GURSKI, Remi

IPC: H04B1/40 ,  G06F13/24

CPC classification number: H04B1/406

Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

Abstract translation: 调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。 每个WCSMSC接收由多个可编程定时器中相应的一个生成的控制信号。 每个定时器从挂钟计数器接收相同的计数值序列。 控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。 处理器还可以编程定时器以产生周期性控制信号。 当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。 通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

公开(公告)号：WO2002091611A1

公开(公告)日：2002-11-14

申请号：PCT/US2002/013955

申请日：2002-05-03

Applicant: QUALCOMM INCORPORATED

Inventor： AGRAWAL, Avneesh ,  LIN, Jeremy, H.

IPC: H04B1/707

CPC classification number: H04B1/7117 ,  H04B1/7115 ,  H04B2201/70707

Abstract: Techniques for increased finger demodulation capability in a hardware efficient manner are disclosed. In one aspect, I and Q samples are shifted into a parallel-accessible shift register. A plurality of chip samples are accessed from the shift register and operated on in parallel to produce a multi-chip result for a channel each cycle. These multi-chip results can be accumulated and output to a symbol-rate processor on symbol boundaries. The scheduling of shift register access, computation, and accumulation can be scheduled such that the hardware is time-shared to support a large number of channels. In another aspect, time-tracking of a large number of channels can be accommodated through channel-specific indexing of the contents of the shift register file. These aspects, along with various others also presented, provide for hardware efficient chip rate processing capability for a large number of channels, with a high degree of flexibility in deployment of those channels.

Abstract translation: 公开了以硬件有效的方式增加手指解调能力的技术。 在一个方面，I和Q样本被移入并行可访问的移位寄存器。 从移位寄存器访问多个芯片样本，并行操作，以产生每个周期的信道的多芯片结果。 这些多芯片结果可以被累加并输出到符号边界上的符号速率处理器。 可以调度移位寄存器访问，计算和累加的调度，使得硬件是时分的，以支持大量信道。 在另一方面，可以通过针对移位寄存器文件的内容的特定索引来容纳大量信道的时间跟踪。 这些方面以及还提出了各种其他方面，为大量渠道提供硬件高效的芯片速率处理能力，在这些频道的部署方面具有高度的灵活性。

公开(公告)号：WO2010107708A2

公开(公告)日：2010-09-23

申请号：PCT/US2010/027351

申请日：2010-03-15

Applicant: QUALCOMM INCORPORATED ,  MAHESHWARI, Shailesh ,  HSU, Liangchi ,  GHOLMIEH, Aziz ,  KAPOOR, Rohit ,  CHAPONNIERE, Etienne, F. ,  ZHANG, Danlu ,  LIN, Jeremy, H.

Inventor： MAHESHWARI, Shailesh ,  HSU, Liangchi ,  GHOLMIEH, Aziz ,  KAPOOR, Rohit ,  CHAPONNIERE, Etienne, F. ,  ZHANG, Danlu ,  LIN, Jeremy, H.

IPC: H04L1/18 ,  H04L29/08 ,  H04L29/06

CPC classification number: H04L1/1867 ,  H04L1/1896 ,  H04W12/02

公开(公告)号：WO2009142814A1

公开(公告)日：2009-11-26

申请号：PCT/US2009/038053

申请日：2009-03-24

Applicant: QUALCOMM INCORPORATED ,  LIN, Jeremy, H. ,  CHAUDHURI, Arunava ,  CHALLA, Raghu, N. ,  SAMPATH, Hemanth

Inventor： LIN, Jeremy, H. ,  CHAUDHURI, Arunava ,  CHALLA, Raghu, N. ,  SAMPATH, Hemanth

IPC: H04L27/26 ,  H04L5/00

CPC classification number: H04L25/0202 ,  H04L5/0007 ,  H04L5/0023 ,  H04L27/265

Abstract: An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

Abstract translation: 一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。 信道估计装置还可以向共享缓冲器提供中间数据。 中间数据可以是瓦片形式，并且可以从FFT符号数据导出。 此外，中间数据可以存储在共享缓冲器中。 解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。