公开(公告)号：WO2022203809A1

公开(公告)日：2022-09-29

申请号：PCT/US2022/017855

申请日：2022-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： PARK, Hee Jun ,  MAHURIN, Eric, Wayne ,  BLANKEVOORT, Tijmen, Pieter, Frederik

IPC: G06N3/063

Abstract: Various embodiments include methods and devices for processing a neural network by an artificial intelligence (AI) processor. Embodiments may include receiving an AI processor operating condition information, dynamically adjusting an AI quantization level for a segment of a neural network in response to the operating condition information, and processing the segment of the neural network quantization using the adjusted AI quantization level.

公开(公告)号：WO2016014213A1

公开(公告)日：2016-01-28

申请号：PCT/US2015/038013

申请日：2015-06-26

Applicant: QUALCOMM INCORPORATED

Inventor： CODRESCU, Lucian ,  MAHURIN, Eric, Wayne

IPC: G06F9/30

CPC classification number: G06F15/82 ,  G06F9/3001 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3012

Abstract: Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, related circuits, methods, and computer-readable media are disclosed. In one aspect, a vector processor comprises a vector register file providing a plurality of write ports and a plurality of vector registers each providing a plurality of accumulators. The vector processor receives an input data vector. For each of the plurality of write ports, the vector processor executes vector operation(s) for accessing an input data value of the input data vector, and determining, based on the input data value, a register index for a vector register among the plurality of vector registers, and an accumulator index for an accumulator among the plurality of accumulators of the vector register. Based on the register index, a register value is retrieved from the register index, and a scalar operation is performed based on the register value and the accumulator index.

Abstract translation: 公开了使用向量寄存器文件，相关电路，方法和计算机可读介质中的数据索引累加器的矢量处理器的标量运算的并行化。 一方面，向量处理器包括提供多个写入端口的向量寄存器文件和多个向量寄存器，每个向量寄存器提供多个累加器。 向量处理器接收输入数据向量。 对于多个写入端口中的每一个，向量处理器执行用于访问输入数据向量的输入数据值的向量操作，并且基于输入数据值，确定多个写入端口中的向量寄存器的寄存器索引 矢量寄存器的多个累加器中的累加器的累加器索引。 基于寄存器索引，从寄存器索引检索寄存器值，并且基于寄存器值和累加器索引执行标量运算。

公开(公告)号：WO2020055700A1

公开(公告)日：2020-03-19

申请号：PCT/US2019/050118

申请日：2019-09-07

Applicant: QUALCOMM INCORPORATED

Inventor： KALYANAM, Vijay, Kiran ,  MAHURIN, Eric, Wayne

IPC: G06F1/3237 ,  G06F1/30 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3206

Abstract: A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.