公开(公告)号：WO2012125767A1

公开(公告)日：2012-09-20

申请号：PCT/US2012/029129

申请日：2012-03-14

Applicant: QUALCOMM INCORPORATED ,  SRIVASTAVA, Ankit ,  WORLEY, Eugene, R. ,  MIAO, Guoqing ,  QUAN, Xiaohong

Inventor： SRIVASTAVA, Ankit ,  WORLEY, Eugene, R. ,  MIAO, Guoqing ,  QUAN, Xiaohong

IPC: H03F1/52 ,  H01L27/02 ,  H02M3/07

CPC classification number: H03F1/52 ,  H01L27/0285 ,  H02M1/32 ,  H02M3/07

Abstract: Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

Abstract translation: 用于放大器和使用电荷泵的其他电路的静电放电（ESD）保护技术。 在示例性实施例中，响应于在电源电压节点和负输出电压节点之间检测到ESD事件，将第二飞跨电容器节点耦合到负输出电压节点的Vneg开关闭合。 响应于在接地节点和负输出电压节点之间检测到ESD事件，将接地节点耦合到第二飞跨电容器节点的接地开关闭合。 响应于在接地节点和负输出电压节点之间检测到ESD事件，Vneg开关进一步闭合。 公开了用于在耦合到电荷泵的功率放大器的输出处提供片上快速恢复钳位以防止由标准IEC 61000-4-2定义的ESD事件的其它技术。

公开(公告)号：WO2008137992A1

公开(公告)日：2008-11-13

申请号：PCT/US2008/063071

申请日：2008-05-08

Applicant: QUALCOMM Incorporated ,  MIAO, Guoqing

Inventor： MIAO, Guoqing

IPC: H03K19/00

CPC classification number: H03K19/0013

Abstract: A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit.

Abstract translation: 一种方法和装置使模拟集成电路断电。 断电电路电耦合到模拟电路，并且适于响应于接收掉电信号而使模拟电路断电。 节点保护电路电耦合到模拟电路，并且适于在模拟电路中响应于当至少一个预定节点处的电压电位为接收功率下降信号时向模拟电路中的至少一个预定节点提供预定电压电势 不由断电电路决定。

公开(公告)号：WO2012170582A3

公开(公告)日：2012-12-13

申请号：PCT/US2012/041170

申请日：2012-06-06

Applicant: QUALCOMM Incorporated ,  SHAH, Peter J. ,  TALEIE, Shahin Mehdizad ,  GROENEWOLD, Gerrit ,  MIAO, Guoqing ,  SUNG, Eunyung

Inventor： SHAH, Peter J. ,  TALEIE, Shahin Mehdizad ,  GROENEWOLD, Gerrit ,  MIAO, Guoqing ,  SUNG, Eunyung

IPC: H03F3/00 ,  H03F3/45

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

公开(公告)号：WO2009045928A1

公开(公告)日：2009-04-09

申请号：PCT/US2008/078000

申请日：2008-09-26

Applicant: QUALCOMM Incorporated ,  CHILAKAPATI, Uma ,  BAZARJANI, Seyfollah ,  FITZGERALD, Joseph ,  MIAO, Guoqing ,  NELSON, Hui-Ya ,  SIDIQI, Khalid J. ,  HINRICHS, Jeffrey

Inventor： CHILAKAPATI, Uma ,  BAZARJANI, Seyfollah ,  FITZGERALD, Joseph ,  MIAO, Guoqing ,  NELSON, Hui-Ya ,  SIDIQI, Khalid J. ,  HINRICHS, Jeffrey

IPC: H03M1/10 ,  H03M3/04 ,  H03M1/66

CPC classification number: H03M3/384 ,  H03M1/1019 ,  H03M1/66 ,  H03M3/50

Abstract: A digital offset is combined with an audio signal in the digital domain to cancel an output offset caused by one or more analog components processing the same audio signal. In this manner, the offset at the output of the audio signal path (e.g., at a power amplifier output) is reduced or eliminated. Consequently, audible artifacts, such as click-and-pop artifacts, can be reduced or eliminated. In audio devices operating in ground-referenced capless mode, power consumption is reduced because of reduced or eliminated direct current (DC) leakage current through speakers or headsets of such audio devices. In some circumstances, the digital offset in the digital domain may be applied at substantially all times of operation of the audio signal path.

Abstract translation: 数字偏移与数字域中的音频信号组合以消除由处理相同音频信号的一个或多个模拟分量引起的输出偏移。 以这种方式，减少或消除音频信号路径输出处的偏移（例如，在功率放大器输出端）。 因此，可以减少或消除诸如点击和流行伪像的声音伪影。 在以地面参考无盖模式工作的音频设备中，由于减少或消除了通过这种音频设备的扬声器或耳机的直流（DC）泄漏电流，功耗将会降低。 在某些情况下，数字域中的数字偏移可以在音频信号路径的操作的基本上全部被应用。

公开(公告)号：WO2022165486A1

公开(公告)日：2022-08-04

申请号：PCT/US2022/070350

申请日：2022-01-26

Applicant: QUALCOMM INCORPORATED

Inventor： CHAKKIRALA, Subbarao Surendra ,  GALAL, Sherif ,  MIAO, Guoqing

IPC: H02M3/158 ,  H02M1/00

Abstract: Certain aspects of the present disclosure are directed to an apparatus for voltage regulation. The apparatus generally includes a first switch, an inductive element, the first switch being coupled between a first voltage rail and a first terminal of the inductive element, a second switch coupled between a second voltage rail and the first terminal of the inductive element, a third switch coupled between a second terminal of the inductive element and a reference potential node, and a fourth switch coupled between the second terminal of the inductive element and an output node.

公开(公告)号：WO2013142782A2

公开(公告)日：2013-09-26

申请号：PCT/US2013/033482

申请日：2013-03-22

Applicant: QUALCOMM INCORPORATED

Inventor： MEHRABI, Arash ,  DEYERLE, IV, Thurman, S. ,  MIAO, Guoqing

IPC: G05F1/56 ,  H03F3/45

CPC classification number: H03F3/45

Abstract: Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.

Abstract translation: 用于设计跨导体的技术，可配置为具有低跨导。 在一个方面，电压到电流转换模块耦合到1：N电流复制模块。 电压到电流转换模块可以被实现为配置有负反馈以产生通过晶体管的电流的运算放大器，其中这种电流与输入电压和共模参考之间的差成比例。 1：N电流复制模块被配置为将另一晶体管中产生的电流镜像到预定比例，使得输出电流也与输入电压和共模参考之间的差成比例。 在示例性实施例中，驱动输出电流的输出级可被配置为作为A类，B类或AB类放大器工作。

公开(公告)号：WO2012125766A3

公开(公告)日：2012-09-20

申请号：PCT/US2012/029128

申请日：2012-03-14

Applicant: QUALCOMM INCORPORATED ,  QUAN, Xiaohong ,  SRIVASTAVA, Ankit ,  MIAO, Guoqing

Inventor： QUAN, Xiaohong ,  SRIVASTAVA, Ankit ,  MIAO, Guoqing

IPC: H02M3/07

Abstract: Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.

公开(公告)号：WO2021262736A1

公开(公告)日：2021-12-30

申请号：PCT/US2021/038513

申请日：2021-06-22

Applicant: QUALCOMM INCORPORATED

Inventor： KESKIN, Mustafa ,  SRIVASTAVA, Ankit ,  WADHWA, Sameer ,  MIAO, Guoqing

IPC: G11C11/54 ,  G11C5/14 ,  G06N3/04 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C5/145 ,  G11C7/1006 ,  H03M1/66

Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

公开(公告)号：WO2014100520A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/076759

申请日：2013-12-19

Applicant: QUALCOMM INCORPORATED

Inventor： QUAN, Xiaohong ,  SHAH, Peter J. ,  SRIVASTAVA, Ankit ,  MIAO, Guoqing

IPC: H04R29/00

CPC classification number: H04R3/007 ,  H04R29/001

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract translation: 用于感测负载电阻的技术。 在一方面，与负载串联提供感测电阻器。 检测电阻器的每个端子通过开关交替耦合到读出放大器。 检测电阻的第二输入耦合到负载的端子。 交替地测量负载上的电压降和负载+检测电阻两端的电压降。 这些电压降可以被数字化并且用于使用例如数字处理器来计算负载的电阻。

公开(公告)号：WO2012075202A1

公开(公告)日：2012-06-07

申请号：PCT/US2011/062729

申请日：2011-11-30

Applicant: QUALCOMM INCORPORATED ,  MIAO, Guoqing ,  SCOFIELD, William C. ,  HUGUNIN, Derick R. ,  CHEN, Zhenqi

Inventor： MIAO, Guoqing ,  SCOFIELD, William C. ,  HUGUNIN, Derick R. ,  CHEN, Zhenqi

IPC: H03G3/00 ,  H03G3/30 ,  H03M3/00 ,  H03M3/72

CPC classification number: H03G3/001 ,  H03G3/002 ,  H03G3/3005 ,  H03G3/3089 ,  H03M3/51

Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract translation: 在信号处理路径中进行自适应增益调整的技术，以实现更大的动态范围。 在示例性实施例中，基于检测到的数字输入信号的电平将数字增益应用于数字输入信号。 相应的模拟增益被应用于数模转换器的输出，用于将数字输入信号转换为模拟信号，数字增益和模拟增益的乘积保持恒定。 在示例性实施例中，采用零交叉检测器仅在信号中检测到的过零点附近更新数字和模拟增益。 在另一示例性实施例中，使用峰值检测器来即时调整数字和模拟增益，以避免信号路径中的限幅。