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    DIGITAL COMPUTE IN MEMORY
    1.
    发明申请
    DIGITAL COMPUTE IN MEMORY 审中-公开

    公开(公告)号：WO2023015167A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/074399

    申请日：2022-08-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： WANG, Zhongze ,  BADAROGLU, Mustafa

    IPC: G11C7/10 ,  G06F7/527 ,  G06N3/063 ,  G11C11/54

    Abstract: Certain aspects generally relate to performing machine learning tasks, and in particular, to computation-in-memory architectures and operations. One aspect provides a circuit for in-memory computation. The circuit generally includes multiple bit-lines, multiple word-lines, an array of compute-in-memory cells, and a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines. Each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network.

    METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS
    3.
    发明申请
    METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS 审中-公开

    公开(公告)号：WO2022115633A1

    公开(公告)日：2022-06-02

    申请号：PCT/US2021/060862

    申请日：2021-11-24

    Applicant: HSU, Fu-Chang ,  HSU, Kevin

    Inventor： HSU, Fu-Chang ,  HSU, Kevin

    IPC: G06N3/063 ,  G06F9/30 ,  G06F15/18 ,  G11C11/22 ,  G11C11/34 ,  G11C11/54

    Abstract: Methods and apparatus for neural network arrays are disclosed. In an embodiment, a neural network array includes a plurality of strings, each string having a drain select gate transistor connected to a plurality of non-volatile memory cells that are connected in series and function as synapses, and a plurality of output nodes, each output node connected to receive output signals from a plurality of drain terminals of the drain select gates. The array also includes a plurality of input nodes, each input node connected to provide input signals to a plurality of gate terminals of the drain select gates, and a plurality of weight select signals connected to the plurality of non-volatile memory cells in each string, respectively. Each weight select signal provides a selected voltage to a selected non-volatile memory cell to cause the selected non-volatile memory cell to conduct current according to a selected characteristic of the selected non-volatile memory cell.

    深层神经网络权重存储器件及其制备方法、电子装置
    4.
    发明申请
    深层神经网络权重存储器件及其制备方法、电子装置 审中-公开

    公开(公告)号：WO2022110343A1

    公开(公告)日：2022-06-02

    申请号：PCT/CN2020/136441

    申请日：2020-12-15

    Applicant: 光华临港工程应用技术研发（上海）有限公司

    Inventor： 孔繁生 ,  周华

    IPC: G11C11/54 ,  G06N3/063 ,  G06N3/08

    Abstract: 本发明公开了一种深层神经网络权重存储器件及其制备方法、电子装置。所述深层神经网络权重存储器件，包括：多条延第一方向设置的第一输入线、多条延第一方向设置的第二输入线和多条延第二方向设置的输出线，以及位于所述第一输入线、所述第二输入线和所述输出线交叉的节点处的数个权重单元，每一所述权重单元均包括：第一晶体管、第二晶体管和存储元件；所述第一晶体管的第一源极与所述第一输入线连接，所述第二晶体管的第二源极与所述第二输入线连接，所述第一晶体管的第一漏极、所述第二晶体管的第二漏极与所述存储元件的第一端连接，所述存储元件的第二端与所述输出线连接。所述神经网络权重存储器件的准确性极大提高。

    MEMRISTIVE DEVICE
    6.
    发明申请
    MEMRISTIVE DEVICE 审中-公开

    公开(公告)号：WO2021167798A1

    公开(公告)日：2021-08-26

    申请号：PCT/US2021/016676

    申请日：2021-02-04

    Applicant: RAIN NEUROMORPHICS INC.

    Inventor： KENDALL, Jack David

    IPC: G11C11/54

    Abstract: A memristive device and mechanisms for providing and using the memristive device are described. The memristive device includes a nanowire, a plurality of memristive plugs and a plurality of electrodes. The nano wire has a conductive core and an insulator coating at least a portion of the conductive core. The insulator has a plurality of apertures therein. The memristive plugs are for the apertures. At least a portion of each of the memristive plugs resides in each of the apertures. The memristive plugs are between the conductive core and the electrodes.

    NON-VOLATILE MEMORY ON CHIP
    8.
    发明申请
    NON-VOLATILE MEMORY ON CHIP 审中-公开

    公开(公告)号：WO2021084225A1

    公开(公告)日：2021-05-06

    申请号：PCT/GB2020/052366

    申请日：2020-09-30

    Applicant: ARM LIMITED

    Inventor： IRBY, Joel Thornton ,  ELSASSER, Wendy Arnott ,  BHARGAVA, Mudit ,  CHONG, Yew Keong ,  LATTIMORE, George McNeil ,  DODRILL, James Dennis

    IPC: G01R31/3185 ,  G01R31/3187 ,  G11C11/54 ,  G11C29/12 ,  G11C29/32 ,  G11C29/44

    Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

    半導体装置
    9.
    发明申请
    半導体装置 审中-公开

    公开(公告)号：WO2021053453A1

    公开(公告)日：2021-03-25

    申请号：PCT/IB2020/058318

    申请日：2020-09-08

    Applicant: 株式会社半導体エネルギー研究所

    Inventor： 青木健 ,  上妻宗広 ,  藤田雅史 ,  石津貴彦

    IPC: G06F12/00 ,  G11C11/54

    Abstract: 演算装置とメモリ間のデータ転送に要するエネルギーを削減した半導体装置を提供する。 半導体装置は、周辺回路およびメモリセルアレイを有する。周辺回路は、メモリセルアレイの駆動回路および制御回路としての機能と、演算機能とを有する。周辺回路は、センスアンプ回路および演算回路を有し、メモリセルアレイは、メモリセルおよびビット線を有する。センスアンプ回路は、ビット線のハイレベルまたはローレベルを判定する機能を有し、その結果を演算回路に出力する。演算回路は、積和演算を行う機能を有し、その結果は半導体装置から出力される。

    PROGRAMMABLE CIRCUITS FOR PERFORMING MACHINE LEARNING OPERATIONS ON EDGE DEVICES
    10.
    发明申请
    PROGRAMMABLE CIRCUITS FOR PERFORMING MACHINE LEARNING OPERATIONS ON EDGE DEVICES 审中-公开

    公开(公告)号：WO2021041526A1

    公开(公告)日：2021-03-04

    申请号：PCT/US2020/047975

    申请日：2020-08-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： YANG, Haining ,  CHIDAMBARAM, Periannan

    IPC: G11C17/16 ,  G11C11/54 ,  G11C11/56 ,  G11C17/18 ,  G06N3/063

    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.

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