公开(公告)号：WO2014169025A1

公开(公告)日：2014-10-16

申请号：PCT/US2014/033474

申请日：2014-04-09

Applicant: QUALCOMM INCORPORATED

Inventor： SPEIER, Thomas, Philip ,  ROBINSON, Eric, F. ,  GANASAN, Jaya, Prakash Subramaniam ,  SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris

IPC: G06F12/08 ,  G06F15/173

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/173

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

Abstract translation: 针对具有两个或更多个处理器的多处理器描述技术，这增加了独占命令以独占状态取高速缓存行的机会，这导致执行存储排他时的性能提高。 读取优先排序的新的总线操作被用作对请求主机可能存储到高速缓存行的其他高速缓存的提示，并且如果可能的话，其他高速缓存应该给排队。 在大多数情况下，这将导致其他主人员排队，并且请求的主人将线独占。 在大多数情况下，两个或多个处理器不会同时对同一地址执行信号量管理序列。 因此，请求主机的负载独占能够在独占状态下取高速缓存行增加次数。

公开(公告)号：WO2015034667A1

公开(公告)日：2015-03-12

申请号：PCT/US2014/051712

申请日：2014-08-19

Applicant: QUALCOMM INCORPORATED

Inventor： MCDONALD, Joseph, G. ,  GANASAN, Jaya, Prakash, Subramaniam ,  SPEIER, Thomas, Philip ,  ROBINSON, Eric, F. ,  PANAVICH, Jason, Lawrence ,  TRUONG, Thuong, Q.

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0824 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache "hit" in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.

Abstract translation: 低延迟高速缓存干预机制实现了窥探过滤器来动态地选择用于计算机系统的多处理器架构中的高速缓存“命中”的intervener缓存。 干扰器的选择基于诸如延迟，拓扑，频率，利用率，负载，磨损平衡和/或计算机系统的功率状态等变量。