公开(公告)号：WO2014149093A1

公开(公告)日：2014-09-25

申请号：PCT/US2013/074480

申请日：2013-12-11

Applicant: SYNOPSYS, INC.

Inventor： DUBEY, Prashant ,  AHUJA, Gaurav ,  YADAV, Sanjay, Kumar ,  KHANUJA, Amit

IPC: G11C7/06 ,  G11C11/24 ,  G11C17/04

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/417 ,  H02M3/07

Abstract: An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.

Abstract translation: 用于产生负位线电压的集成电路包括可连接到存储器单元的位线和连接到位线的以组为单位的多个电容器。 步进信号发生器可以产生要施加到一组电容器的步进信号的连续序列。 电路可以是集成存储器电路器件的一部分，以将位线驱动到负电压以实现写辅助方案。

公开(公告)号：WO2014197004A1

公开(公告)日：2014-12-11

申请号：PCT/US2013/069016

申请日：2013-11-07

Applicant: SYNOPSYS, INC.

Inventor： DUBEY, Prashant ,  MITTAL, Shivangi ,  JHA, Raushan, Kumar

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  G06F1/12 ,  H03K3/35625 ,  H04L7/0338

Abstract: A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUTl) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUTl, DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUTl, DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.

Abstract translation: 数据存储元件包括具有第一和第二锁存器（LI，L2），错误级（ES）和从级（SLS）的主级（MS）。 基于相对于第一阈值电平（TP1）的输入信号（DATA），第一锁存器（LI）以时钟方式基于时钟信号（CLK，CLKT，CLKB）产生第一逻辑信号（DOUT1）。 基于相对于第二阈值电平（TP2）的输入信号（DATA），第二逻辑信号（DOUT2）基于时钟信号（CLK，CLKT，CLKB）以时钟方式产生（L2）。 第二阈值水平（TP2）与第一阈值水平（TP1）不同。 如果第一和第二逻辑信号（DOUT1，DOUT2）具有相同的逻辑状态，则误差级提供具有第一逻辑状态的误差信号（ER），并且具有第二逻辑状态，它们具有不同的逻辑状态。 当错误信号（ER）具有第一逻辑状态时，从属级（SLS）将数据存储元件的输出值（Q）设置为第一和第二逻辑信号（DOUT1，DOUT2）的公共逻辑状态，以及 保持输出值（Q）不变。