公开(公告)号：WO2019085931A1

公开(公告)日：2019-05-09

申请号：PCT/CN2018/112907

申请日：2018-10-31

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： SHEN, Jian Hung

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C5/066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/107

Abstract: A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output terminal communicatively connected to the deserializer, the CTLE configured to perform a channel gain compensation on the input signal received by the first input terminal and to transmit the compensated input signal to the deserializer. The RAM may further comprise a decision feedback equalizer (DFE) including a second input terminal communicatively connected to the CTLE and a second output terminal communicatively connected to the deserializer, the DFE configured to reduce an inter-symbol interference (ISI) of the input signal.

公开(公告)号：WO2016200446A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/019049

申请日：2016-02-23

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： MOSCALUK, Gary ,  GEORGESCU, Bogdan ,  WILLIAMS, Timothy

IPC: H03K17/687 ,  G11C16/02 ,  G11C16/30

CPC classification number: H03K17/04123 ,  G11C5/147 ,  G11C5/148 ,  G11C7/1084 ,  G11C11/2297 ,  G11C11/417 ,  G11C16/30 ,  G11C17/08 ,  H03K3/356182 ,  H03K19/017 ,  H03K19/018507

Abstract: A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

Abstract translation: 偏置电路包括包括第一晶体管和第二晶体管的级联晶体管。 第一晶体管的第一栅极在第一节点耦合到第二晶体管的第二栅极。 电路还包括耦合到第一晶体管或第二晶体管中的至少一个的电压控制电路。 电压控制电路被配置为根据输入信号的状态变化而改变第一晶体管或第二晶体管中的至少一个的电压电平，以允许输出信号的电压域转变，而不会使输入信号的电源信号 偏置电路。

公开(公告)号：WO2016029341A1

公开(公告)日：2016-03-03

申请号：PCT/CN2014/085093

申请日：2014-08-25

Applicant: MICRON TECHNOLOGY, INC. ,  CHU, Weilu

Inventor： CHU, Weilu

IPC: H03F3/16

CPC classification number: H03K3/356 ,  G11C7/1084 ,  G11C29/50 ,  G11C2029/5004 ,  H03F3/347

Abstract: An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. The first stage is configured to receive an input voltage and produce an intermediate voltage as an output. The second stage is configured to receive the intermediate voltage and provide an output voltage that is equal to the input voltage. The voltage buffer may be coupled to a current source. The second stage of the voltage buffer may have current drive ability.

Abstract translation: 描述了用于缓冲​​来自电路的电压而不具有当前驱动能力的装置和方法。 示例性设备包括包括两个相同级的电压缓冲器。 第一级配置为接收输入电压并产生中间电压作为输出。 第二级被配置为接收中间电压并提供等于输入电压的输出电压。 电压缓冲器可以耦合到电流源。 电压缓冲器的第二级可能具有电流驱动能力。

公开(公告)号：WO2015191238A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/031147

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry ,  BRUNOLLI, Michael Joseph

IPC: G11C7/10 ,  G06F13/42 ,  H04L25/02 ,  G11C5/06 ,  H03K19/0185 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/02

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G06F13/4243 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  H03K19/018521 ,  H03K19/018528 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract translation: 提供源同步系统，其中在数据源端点以及数据宿端点中可能存在非均匀接口。

公开(公告)号：WO2014149093A1

公开(公告)日：2014-09-25

申请号：PCT/US2013/074480

申请日：2013-12-11

Applicant: SYNOPSYS, INC.

Inventor： DUBEY, Prashant ,  AHUJA, Gaurav ,  YADAV, Sanjay, Kumar ,  KHANUJA, Amit

IPC: G11C7/06 ,  G11C11/24 ,  G11C17/04

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/417 ,  H02M3/07

Abstract: An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.

Abstract translation: 用于产生负位线电压的集成电路包括可连接到存储器单元的位线和连接到位线的以组为单位的多个电容器。 步进信号发生器可以产生要施加到一组电容器的步进信号的连续序列。 电路可以是集成存储器电路器件的一部分，以将位线驱动到负电压以实现写辅助方案。

公开(公告)号：WO2012030497A1

公开(公告)日：2012-03-08

申请号：PCT/US2011/047430

申请日：2011-08-11

Applicant: MICRON TECHNOLOGY INC. ,  HUBER, Brian

Inventor： HUBER, Brian

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/10 ,  G11C7/1084

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract translation: 公开了在信号节点处提供和接收非数据信号的存储器和方法。 一个这样的存储器包括第一和第二信号节点以及第一和第二信号缓冲器。 第一信号缓冲器被配置为响应于第一数据选通信号而工作，并且还被配置为响应于非数据信号而工作。 第二信号缓冲器被配置为响应于第二数据选通信号而工作。 示例性的第一数据选通信号是由存储器提供的读数据选通信号。 在另一示例中，第一数据选通信号是由存储器接收的写数据选通信号。 非数据信号的示例包括数据屏蔽信号，数据有效信号，纠错信号以及其它信号。

公开(公告)号：WO2008148197A1

公开(公告)日：2008-12-11

申请号：PCT/CA2008/001069

申请日：2008-06-06

Applicant: MOSAID Technologies Incorporated ,  MILLAR, Bruce

Inventor： MILLAR, Bruce

IPC: H03H7/38 ,  G11C11/407 ,  G11C7/10 ,  G11C7/12 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an "on" output is to be generated, and the pull-down network is configured to produce a calibrated drive impedance when an "off" output is to be generated. In termination mode, the pull- up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance, respectively, such that together they form a split termination.

Abstract translation: 提供了执行片外驱动（OCD）和片上终止（ODT）的系统和方法。采用由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络来实现这两个功能。 在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，下拉网络被配置为产生校准的驱动阻抗 生成。 在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

公开(公告)号：WO2008082606A1

公开(公告)日：2008-07-10

申请号：PCT/US2007/026414

申请日：2007-12-28

Applicant: SPANSION LLC ,  KURIHARA, Kazuhiro

Inventor： KURIHARA, Kazuhiro

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C5/066 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06

Abstract: The present invention provides a semiconductor device and a method of controlling the semiconductor device, the semiconductor device comprising: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal comprising: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is comprised of the entire remaining portion of the address data not comprising the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first internal address line or the second internal address line, when the address data is input to the terminal.

Abstract translation: 本发明提供一种半导体器件及其控制方法，所述半导体器件包括：存储单元阵列; 输入或输出存储在存储单元阵列中的存储数据的终端，并且输入指示存储单元阵列中存​​储数据被输入或输出的地址的地址数据，该终端包括：第一终端，其输入第一部分 地址数据; 以及输入所述地址数据的第二部分的第二终端，其中所述地址数据的第二部分包括不包括所述地址数据的第一部分的地址数据的整个剩余部分; 提供地址数据的第一内部地址线和第二内部地址线; 以及根据预定的开关信息将地址数据的第一部分耦合到第一内部地址线或第二内部地址线之一的开关，同时将第二部分地址数据耦合到第一内部地址线中的另一个 地址线或第二个内部地址线，当地址数据输入终端时。

公开(公告)号：WO2006072094A8

公开(公告)日：2007-04-26

申请号：PCT/US2005047671

申请日：2005-12-28

Applicant: SEMI SOLUTIONS LLC

Inventor： KAPOOR ASHOK ,  STRAIN ROBERT ,  MARKO REUVEN

IPC: H01L29/76

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/404 ,  G11C16/0408 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/783

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管具有区域效率，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管的漏电保持在较小的值。 在ON状态下，阈值电压设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 本发明对于SRAM，DRAM，NVM器件和其他存储器单元更有用。

公开(公告)号：WO2006072094A2

公开(公告)日：2006-07-06

申请号：PCT/US2005047671

申请日：2005-12-28

Applicant: SEMI SOLUTIONS LLC

Inventor： KAPOOR ASHOK ,  STRAIN ROBERT ,  MARKO REUVEN

IPC: H01L29/76

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/404 ,  G11C16/0408 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/783

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管是面积有效的，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管漏电保持在较小值。 在ON状态下，阈值电压被设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 本发明对于SRAM，DRAM，NVM器件和其它存储器单元更有用。