公开(公告)号：WO2016057138A1

公开(公告)日：2016-04-14

申请号：PCT/US2015/048200

申请日：2015-09-02

Applicant: SYNOPSYS, INC.

Inventor： LARZUL, Ludovic, Marc ,  EMIRIAN, Frederic, Maxime

IPC: G06F9/455

CPC classification number: G06F17/5027 ,  G06F17/5036 ,  G06F2217/78

Abstract: Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number.

Abstract translation: 实施例涉及电路的仿真以及用于执行功率分析的仿真电路中的信号的跟踪状态。 主机系统将功率分析逻辑并入被测设计（DUT）。 仿真器模拟DUT以及并入的功率分析逻辑。 基于功率分析逻辑，在功率分析时钟周期期间，仿真器从DUT的多个信号中选择信号。 仿真器确定是否检测到所选信号的状态事件。 如果检测到状态事件，则针对所选择的信号更新状态计数，该信号指示在DUT的仿真期间针对所选择的信号检测到的状态事件的数量。 如果状态计数基于更新达到阈值数，则仿真器向主机系统发送指示状态计数达到阈值数的计数更新信号。