公开(公告)号：WO1990001192A1

公开(公告)日：1990-02-08

申请号：PCT/US1989003044

申请日：1989-07-18

Applicant: UNITED STATES DEPARTMENT OF ENERGY

Inventor： UNITED STATES DEPARTMENT OF ENERGY ,  DAVIDSON, George, Sidney ,  GRAFE, Victor, Gerald

IPC: G06F09/30

CPC classification number: G06F9/4494

Abstract: A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output adress; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ''fire'' signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Abstract translation: 公开了一种利用数据驱动的处理器节点架构的数据流计算机和计算方法。 优选实施例中的装置包括多个先进先出（FIFO）寄存器，多个相关数据流存储器和处理器。 处理器进行必要的计算，并包括一个控制单元来产生信号，使相应的FIFO寄存器能够接收结果。 在特定实施例中，每个节点有三个FIFO寄存器：输入FIFO寄存器，用于从外部源接收输入信息并将其提供给数据流存储器; 输出FIFO寄存器，用于从处理器向外部接收者提供输出信息; 以及内部FIFO寄存器，用于将来自处理器的信息提供回数据流存储器。 数据流存储器由四个通常被寻址的存储器组成。 参数存储器保存计算中使用的A和B参数; 操作码存储器保存指令; 目标存储器保存输出地址; 标签存储器包含每个参数的状态位。 一个状态位指示相应的参数是否在参数存储器中，并且一个状态，而是指示是否重新使用相应数据参数中存储的信息。 当所有必要信息已经存储在数据流存储器中时，标签存储器输出“火”信号（信号R VALID），并且因此当指令准备被触发到处理器时。