公开(公告)号：WO2023001715A1

公开(公告)日：2023-01-26

申请号：PCT/EP2022/069928

申请日：2022-07-15

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： NIU, Shengpu ,  LAMBRECHT, Joris ,  VERPLAETSE, Michiel ,  XIN, Yin

IPC: H03M1/08 ,  H03M1/12

Abstract: The present disclosure relates to a sampling circuit for sampling an analog input signal comprising: a capacitive means, a reset switch, and a sampling switch; the reset switch and the sampling switch being connected to a signal generator circuit configured to provide periodic reset and sampling control signals to the respective switches for controlling their operation; wherein the respective periodic reset and sampling control signals have equal duty factors and signal periods, and a phase delay with respect to one another being less than the signals' duty factor, thereby forming an overlap period during which the reset switch and the sampling switch remain closed.