公开(公告)号：WO2023036609A1

公开(公告)日：2023-03-16

申请号：PCT/EP2022/073535

申请日：2022-08-24

申请人： ROBERT BOSCH GMBH

发明人： KIRCHNER, Tobias ,  SOLIMAN, Taha

IPC分类号： H03M1/12 ,  H03M1/42 ,  H03M1/46

摘要： Vorrichtung aufweisend einen ersten Eingang zum Empfangen eines Eingangsstroms, einen zweiten Eingang zum Empfangen eines Referenzstroms, und einen ersten Ausgang, wobei die Vorrichtung dazu ausgebildet ist, den Eingangsstrom mit dem Referenzstrom zu vergleichen und, basierend auf dem Vergleich, einen Ausgangsstrom an dem ersten Ausgang auszugeben.

公开(公告)号：WO2023003959A1

公开(公告)日：2023-01-26

申请号：PCT/US2022/037729

申请日：2022-07-20

申请人： MARVELL ASIA PTE LTD

发明人： NGUYEN, Ray Luan ,  FAN, Nong ,  ALAM, Dawood ,  HATCHER, Geoffrey ,  AZARMNIA, Morteza

IPC分类号： H04L25/14 ,  H04B1/04 ,  H03M9/00 ,  H04L25/03 ,  G06F17/14 ,  H04B17/21 ,  H03M1/12

摘要： A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.

公开(公告)号：WO2023278923A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/072698

申请日：2022-06-01

申请人： QUALCOMM INCORPORATED

发明人： MEHDIZAD TALEIE, Shahin ,  SEO, Dongwon ,  SWAMINATHAN, Ashok ,  SAHOTA, Gurkanwal Singh ,  WEIL, Andrew ,  FEI, Haibo

IPC分类号： H03M1/74 ,  H03M1/12 ,  H03M1/78 ,  H03M1/002 ,  H03M1/1295 ,  H03M1/466 ,  H03M1/502 ,  H03M1/742 ,  H03M1/747 ,  H03M1/785

摘要： Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

公开(公告)号：WO2022271180A1

公开(公告)日：2022-12-29

申请号：PCT/US2021/039028

申请日：2021-06-25

申请人： INTEL CORPORATION

发明人： CAMPONESCHI, Matteo ,  CLARA, Martin ,  MOLINA, Albert ,  RAJAMANI, Kannan

IPC分类号： H03M1/12 ,  H03M1/10

摘要： An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

公开(公告)号：WO2022271066A1

公开(公告)日：2022-12-29

申请号：PCT/SE2022/050608

申请日：2022-06-21

申请人： SAAB AB

发明人： WALLIN, Thomas ,  GITYE, Gabriel ,  OLSSON, Rune

IPC分类号： H04W56/00 ,  H04B17/21 ,  H04J3/06 ,  H03M1/12

摘要： The present disclosure relates to a method (100) for synchronizing time alignment in a multi-channel radio frequency receiving system, the method comprising injecting (101) an amplitude modulated reference signal into each channel in the multi-channel receiver at a location associated with each antenna input. Further, the method comprises the steps of detecting (102) a position of the reference signal within a time sample window and determining (103) propagation time difference between each channel within the receiver electronics. Further, the method comprises the steps of determining (104) adjustment parameters, for synchronizing time alignment, for each channel and adjusting (105) the channels in the time domain in accordance with the determined adjustment parameters of synchronization for each channel.

公开(公告)号：WO2022230105A1

公开(公告)日：2022-11-03

申请号：PCT/JP2021/016967

申请日：2021-04-28

申请人： 日本電信電話株式会社

发明人： 北　翔太 ,  納富　雅也 ,  野崎　謙悟 ,  新家　昭彦

IPC分类号： H03M1/12

摘要： 本発明のアナログ・デジタル変換方法は、光アナログ信号を電気デジタル信号に変換するアナログ・デジタル変換方法であって、光アナログ信号について、第１の参照光でのアフィン変換と、第２の参照光の検波軸でのホモダイン検波との少なくともいずれか一方を実施するステップと、実施された光アナログ信号を、光電変換によって電気アナログ信号に変換するステップと、電気アナログ信号をしきい値処理により電気デジタル信号に変換するステップとを備える。　これにより、本発明のアナログ・デジタル変換方法は、消費電力を低減できる。

公开(公告)号：WO2022213844A1

公开(公告)日：2022-10-13

申请号：PCT/CN2022/083620

申请日：2022-03-29

申请人： 大唐恩智浦半导体（徐州）有限公司

发明人： 斯高腾彼得

IPC分类号： H03M1/12

摘要： 一种Sigma-Delta模数转换器及其控制方法，Sigma-Delta模数转换器包括积分单元和比较单元，积分单元具有固定的第一参考信号，比较单元具有可变的第二参考信号，第二参考信号的幅值与模数转换器的输入模拟信号的幅值成正比。通过为比较单元提供可变的第二参考信号，模数转换器具有了较大的摆幅空间，较大的摆幅空间既可以降低电源电压，还可以减小电容尺寸，从而减小模数转换器所需的面积。

公开(公告)号：WO2022212002A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/019904

申请日：2022-03-11

申请人： BEIJING VOYAGER TECHNOLOGY CO., LTD. ,  LU, Yue

发明人： CHAWLA, Vipul ,  WANG, Youmin

IPC分类号： G01S7/4861 ,  G01S17/894 ,  G01S17/931 ,  B60W40/02 ,  H03M1/12 ,  B60W50/00 ,  G01J1/44

摘要： Apparatus and methods for reducing inter symbol interference from reflected laser pulses that are received close in time. A laser is provided to emit a laser beam pulse. A photodetector is mounted to receive a reflected laser beam pulse after reflecting off an object in an external environment, and produce a voltage signal corresponding to the reflected laser beam pulse. The voltage signal is provided to a delay path circuit having a delay line and a gain control circuit to provide a delayed, reduced amplitude voltage signal. The delayed, reduced amplitude voltage signal is subtracted from the voltage signal in a subtraction circuit to produce a truncated pulse. The output of the subtraction circuit is provided to a pulse detector circuit to detect the arrival time of the leading edge of the truncated pulse.

公开(公告)号：WO2022122288A1

公开(公告)日：2022-06-16

申请号：PCT/EP2021/081318

申请日：2021-11-11

申请人： AMS SENSORS GERMANY GMBH [DE]/[DE]

发明人： ADUSUMALLI, Ravi Kumar ,  THOTTATHIL, Rahul

IPC分类号： G01J1/42 ,  G01J1/44 ,  H03M1/12

摘要： In one embodiment an optical sensing arrangement comprises a first sensor (D1) configured to provide a first sensor signal (I1), a second sensor (D2) configured to provide a second sensor signal (I2), an integration unit (20) comprising a first input (21) which is connected to the first sensor (D1), a second input (22) which is connected to the second sensor (D2), a first output (23) which is configured to provide a first integration signal (V1) as a function of the first sensor signal (I1), and a second output (24) which is configured to provide a second integration signal (V2) as a function of the second sensor signal (I2), a comparing unit (30) comprising a first input (31) which is connected to the first output (23) of the integration unit (20), a second input (32) which is connected to the second output (24) of the integration unit (20) and an output (33) configured to provide a comparison signal (CMP) as a function of the first and the second integration signal (V1, V2), and a control unit (40) comprising a first input (41) which is coupled to the output (33) of the comparing unit (30), wherein the control unit (40) is configured to evaluate pulses of the comparison signal (CMP) and therefrom provide an output count indicative of a difference between the first and the second sensor signal (I1, I2).

公开(公告)号：WO2022116414A1

公开(公告)日：2022-06-09

申请号：PCT/CN2021/082548

申请日：2021-03-24

申请人： 深圳市紫光同创电子有限公司

发明人： 游光耀 ,  梁远军

IPC分类号： H03M1/12

摘要： 一种高速采样电路，包括采样模块、锁存模块、第一控制模块、第二控制模块和第三控制模块，该采样模块，用于将差分输入信号进行放大；该锁存模块，用于将该采样模块的差分输出信号进行锁存；该第一控制模块，用于在第一时钟信号下控制该采样模块；该第二控制模块，用于在第二时钟信号下控制该锁存模块；该第三控制模块，用于在第二时钟信号下控制差分输出信号输出。该高速采样电路，采样模块采样差分输入信号后，输出给锁存模块，并控制锁存模块输出差分输出信号，相较于现有技术的两级采样模块，节省了第二级采样模块的传输延时，可以提高信号的高速采样带的性能。