公开(公告)号：WO2016097793A1

公开(公告)日：2016-06-23

申请号：PCT/IB2014/003173

申请日：2014-12-14

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： COL, Gerard, M. ,  EDDY, Colin ,  GLENN, Henry, G.

IPC: G06F15/163

CPC classification number: G06F9/3855 ,  G06F9/30043 ,  G06F9/3836 ,  G06F13/36 ,  Y02D10/14

Abstract: An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.

Abstract translation: 一种装置包括第一和第二保留站。 第一保留站（421.L）调度负载微指令，并且在保持总线（444）上指示负载微指令是否是指定的负载微指令，用于从除核心缓存之外的规定资源检索操作数 记忆。 第二保留站（421.1-421.N）被耦合到保持总线（444），并在其中分派一个或多个依赖于负载微指令执行的一个或多个较小的微指令，以在第一个 加载微指令，并且如果在保持总线（444）上指示负载微指令是指定的负载微指令，则第二保留站（421.1-421.N）被配置为停止一个或多个更年轻的 微指令，直到加载微指令已经检索到操作数。 多个非核心资源包括经由控制总线耦合到失序处理器的控制元件。

公开(公告)号：WO2015177595A1

公开(公告)日：2015-11-26

申请号：PCT/IB2014/003259

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： GLENN, Henry, G. ,  JAIN, Dinesh, K. ,  GASKINS, Stephan

IPC: G11C17/00

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and stores decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract translation: 一种装置包括装置编程器和多个核。 编程器对具有压缩配置数据的半导体熔丝阵列进行编程。 多个核心中的每个核心在加电/复位时访问熔丝阵列以读取和解压缩压缩数据，并且将存储器中的一个或多个高速缓冲存储器的解压缩数据集存储在多个核心的每一个中，该存储器耦合到 多个核心中的每一个。 多个核心中的每一个具有复位逻辑和睡眠逻辑。 复位逻辑采用解压缩数据集在上电/复位时初始化一个或多个高速缓存存储器。 休眠逻辑确定在电源门控事件之后恢复电力，并且随后访问商店以检索和使用解压缩数据集来初始化电源门控事件之后的一个或多个高速缓存。