公开(公告)号：WO2017058457A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/049990

申请日：2016-09-01

Applicant: XILINX, INC.

Inventor： AGGARWAL, Rajat ,  WANG, Zhiyong ,  LU, Ruibing ,  DAS, Sabyasachi

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: In one embodiment of the invention, a processor-implemented method is provided for placing and routing a circuit design (102). A first netlist is generated for a circuit design. Placement is performed (108) for the first netlist (106) on a target IC to produce a first placed design (1 10). A set of optimizations are performed (1 12) on the first placed design. The set of optimizations are recorded (1 14) in an optimization history file (1 16). One or more optimizations specified in the optimization history file are performed (1 18/202) on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed (206) for the second netlist on the target IC to produce a second placed design (208) that is different than the first placed design. Nets of the second placed design are routed (210) to produce a placed and routed circuit design.

Abstract translation: 在本发明的一个实施例中，提供了一种用于放置和布线电路设计（102）的处理器实现的方法。 生成电路设计的第一个网表。 对目标IC上的第一网表（106）执行放置（108）以产生第一放置设计（110）。 在首次放置的设计中执行一组优化（112）。 在优化历史文件（116）中记录优化集（114）。 在第一网表上执行在优化历史文件中指定的一个或多个优化（18/202）以产生与第一网表不同的第二网表。 对目标IC上的第二网表执行放置（206），以产生与第一放置设计不同的第二放置设计（208）。 第二放置设计的网络被路由（210）以产生放置和路由的电路设计。

公开(公告)号：WO2018136156A1

公开(公告)日：2018-07-26

申请号：PCT/US2017/064026

申请日：2017-11-30

Applicant: XILINX, INC.

Inventor： NG, Aaron ,  DAS, Sabyasachi ,  BASU, Prabal

IPC: G06F17/50

Abstract: Physical synthesis for a circuit design can include determining (320), using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing (330) the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate effectiveness of a first physical synthesis optimization, and selectively performing (335, 340), using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.