公开(公告)号：WO2014171977A1

公开(公告)日：2014-10-23

申请号：PCT/US2013/073683

申请日：2013-12-06

Applicant: XILINX, INC.

Inventor： VO, Thao, H.T. ,  GAN, Andy, H. ,  LI, Xiao-Yu ,  KLEIN, Matthew, H.

IPC: H01L25/065 ,  G06F1/32

CPC classification number: H01L25/0652 ,  G06F1/3203 ,  G06F1/324 ,  G06F17/5045 ,  G06F17/5054 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor package includes an interposer (208, 326, 416, 516) and a plurality of integrated circuit (IC) dice (102-108, 232-234, 322-324, 412-414, 512-514) disposed on and intercoupled via the interposer. A first IC die (102, 232, 322, 412, 512) has a clock speed rating that is greater than a clock speed rating of another (104-108, 234, 324, 414, 514) of the IC dice. A plurality of programmable voltage tuners (1 10-1 16, 202-204, 312 & 316, 402-404, 502-504) are coupled to the plurality of IC dice, respectively. A first voltage tuner (1 10, 202, 312, 402, 502) is coupled to the first IC die (102, 232, 322, 412, 512), and the first voltage tuner is programmed to reduce a voltage level of a voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract translation: 半导体封装包括插入器（208,326,416,516）和多个集成电路（IC）芯片（102-108,232-234,322-324,412-414,512-514），其设置在并联上 通过插入器。 第一IC芯片（102,232,322,412,512）的时钟速度额定值大于IC芯片的另一个时钟速度等级（104-108,234,324,414,514）。 多个可编程电压调谐器（110-116,202-204,312和316,402-404,502-504）分别耦合到多个IC芯片。 第一电压调谐器（110,202,312,402,502）耦合到第一IC管芯（102,232,312,412,512），并且第一电压调谐器被编程以降低电压的电压电平 输入到第一电压调谐器并将降低的电压输出到第一IC芯片。