公开(公告)号：WO2023282888A1

公开(公告)日：2023-01-12

申请号：PCT/US2021/040496

申请日：2021-07-06

Applicant: ZEKU, INC.

Inventor： LOW, Su-lin ,  LI, Yunhong ,  HONG, Hausting ,  LEE, Chun-I ,  KOVOOR, Sheethal ,  MA, Tianan ,  LI, Jianzhou ,  BAGCHI, Sonali ,  PAO, Sammy, Tzu-Kiang ,  CHEN, Na ,  KI, Sangwon ,  WANG, Zengyu ,  SURESHCHANDRAN, Swaminathan ,  WEE, Sun, Hee

IPC: H04W72/04 ,  H04W72/12 ,  H04L29/08

Abstract: According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a buffer configured to receive a DL Layer 2 protocol data unit (PDU) from a Medium Access Control (MAC) circuit. The DL Layer 2 block may also include a microcontroller. The microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active. The microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive. The DL Layer 2 block may further include a DL Layer 2 processing circuit. The DL Layer 2 processing circuit may be configured to fetch the PDU from the buffer when activated. The DL Layer 2 processing circuit may be further configured to perform Layer 2 processing of the PDU.