公开(公告)号：WO2013114398A3

公开(公告)日：2013-10-10

申请号：PCT/IN2013000031

申请日：2013-01-17

Applicant: TATA POWER COMPANY LTD ,  DIKSHIT RAGHUKUL ,  JAIN AKANKSHA

Inventor： DIKSHIT RAGHUKUL ,  JAIN AKANKSHA

IPC: G06F13/00

CPC classification number: G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

Abstract: A Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device overcomes drawbacks known in the art including lack of security due to software based encryption implementation and driver and OS dependency. The USB bridge comprises a Host PHY operating in a Device mode and a Device PHY operating in a Host mode, connected to the USB Host and the USB mass storage device respectively via a bidirectional USB link. The FPGA is connected to each of the Host PHY and the Device PHY via a bidirectional ULPI link respectively. Data from the USB Host is written into the FPGA of the USB bridge through the Host PHY. This data in parallel form is then stored internally and subsequently communicated to the USB mass storage device through the Device PHY over the Device ULPI Interface.

Abstract translation: 用于USB主机和USB大容量存储设备之间的数据通信的基于现场可编程门阵列（FPGA）的USB桥接实现克服了本领域已知的缺点，包括由于基于软件的加密实现和驱动器和OS依赖性而导致的安全性不足。 USB桥包括以设备模式操作的主机PHY和以主机模式操作的设备PHY，分别经由双向USB链路连接到USB主机和USB大容量存储设备。 FPGA分别通过双向ULPI链路连接到主机PHY和设备PHY中的每一个。 USB主机的数据通过主机PHY写入USB桥的FPGA。 然后将并行形式的数据存储在内部，随后通过设备ULPI接口通过设备PHY传送到USB大容量存储设备。

公开(公告)号：WO2011100164A2

公开(公告)日：2011-08-18

申请号：PCT/US2011/023697

申请日：2011-02-04

Applicant: SILICON IMAGE, INC. ,  RUBERG, Alan, T. ,  ISAAC, Roger, D.

Inventor： RUBERG, Alan, T. ,  ISAAC, Roger, D.

IPC: H04L29/10

CPC classification number: G06F13/4204 ,  G06F13/4045 ,  G06F13/4282 ,  H04L29/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Abstract translation: 本发明的实施例一般涉及用于串行和并行通信的混合接口。 一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚， 以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。 该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及 通过第二多个引脚在第二模式中发送或接收串行数据。

公开(公告)号：WO2009146145A2

公开(公告)日：2009-12-03

申请号：PCT/US2009/039583

申请日：2009-04-06

Applicant: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND ON BEHALF OF THE UNIVERSITY OF ARIZONA ,  OHIO UNIVERSITY ,  LOURI, Ahmed ,  ROVEDA, Janet, Meiling Wang ,  KODI, Avinash, K. ,  SARATHY, Ashwini

Inventor： LOURI, Ahmed ,  ROVEDA, Janet, Meiling Wang ,  KODI, Avinash, K. ,  SARATHY, Ashwini

IPC: H04W28/04

CPC classification number: H04L47/41 ,  G06F11/08 ,  G06F13/4045 ,  G06F2213/0038 ,  H04L43/04 ,  H04L47/10 ,  H04L47/12 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures.

Abstract translation: 本发明提供了用于检测和校正网络片上（NoC）架构的路由器间链路中的传输错误的方法。

公开(公告)号：WO2009078544A1

公开(公告)日：2009-06-25

申请号：PCT/KR2008/005180

申请日：2008-09-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  PARK, Hojoon ,  KIM, Jaemyoung

Inventor： PARK, Hojoon ,  KIM, Jaemyoung

IPC: G06F3/023

CPC classification number: G06F13/4045

Abstract: The invention relates to a binary value input/output processing apparatus and method for automatically inputting binary values. A binary value that is inputted first is temporarily stored in a buffer. When a symbol indicating a binary value, such as '0x' or '0X', is detected from the next input character string, the binary value stored in the buffer is automatically outputted to the screen, following the symbol. Then, a user selects to output, to the output device, the binary value automatically outputted to the screen or to output a new binary value to the output device, instead of the binary value. When the new binary value is outputted, the binary value stored in the buffer is deleted, and the new binary value is stored in the buffer.

Abstract translation: 本发明涉及二进制值输入/输出处理装置和方法，用于自动输入二进制值。 首先输入的二进制值被临时存储在缓冲器中。 当从下一个输入字符串中检测到表示二进制值的符号（例如'0x'或'0X'）时，存储在缓冲器中的二进制值将自动输出到跟随该符号的屏幕上。 然后，用户选择向输出设备输出自动输出到屏幕的二进制值，或者向输出设备输出新的二进制值，而不是二进制值。 当输出新的二进制值时，存储在缓冲器中的二进制值被删除，新的二进制值被存储在缓冲器中。

公开(公告)号：WO2009012426A3

公开(公告)日：2009-04-09

申请号：PCT/US2008070405

申请日：2008-07-18

Applicant: WILOCITY LTD ,  MYERS WOLIN LLC ,  ELBOIM YARON

Inventor： ELBOIM YARON

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4045 ,  G06F2213/0026

Abstract: A distributed interconnect bus apparatus for connecting peripheral devices, The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus: and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

Abstract translation: 一种用于连接外围设备的分布式互连总线设备。该设备可用于无线连接外围设备或允许这些设备通过网络的连接。 该设备包括耦合到互连总线的根部分的第一桥接器，以及耦合到互连总线的端点部件的第二桥接器。 所述装置还可以包括用于生成至少ACK信号的确认（ACK）终止; 以及包括至少一个用于临时保存多个不同事务的数据分组的接收缓冲器的流控制机构。

公开(公告)号：WO2008131067A1

公开(公告)日：2008-10-30

申请号：PCT/US2008/060579

申请日：2008-04-17

Applicant: VIDEO PRODUCTS, INC. ,  BICA, Adrian ,  GIERKE, Justin T.

Inventor： BICA, Adrian ,  GIERKE, Justin T.

IPC: G06F13/40

CPC classification number: G06F13/4045

Abstract: A system and method for extending communications between a USB host (108) and a flash media device (110). The system is capable of converting command block wrapper data to SCSI data and sending the converted data over a non-USB communications channel (106), such as a Category 5 cable. The system is further capable of receiving the data sent over the non-USB communications channel (106) and converted the received data back to command block wrapper data prior to sending the data to a flash media device (110).

Abstract translation: 一种用于扩展USB主机（108）和闪存介质设备（110）之间的通信的系统和方法。 该系统能够将命令块包装数据转换为SCSI数据，并通过非USB通信通道（106）（例如5类电缆）发送转换的数据。 该系统还能够在将数据发送到闪存介质设备（110）之前，接收通过非USB通信通道（106）发送的数据并将接收到的数据转换回命令块封装数据。

公开(公告)号：WO2007067191A3

公开(公告)日：2007-09-20

申请号：PCT/US2006001861

申请日：2006-01-19

Applicant: AVOCENT CORP ,  BEASLEY MICHAEL W ,  SHELTON GARY W

Inventor： BEASLEY MICHAEL W ,  SHELTON GARY W

IPC: G06F3/00

CPC classification number: G06F13/4282 ,  G06F13/4045 ,  G06F2213/0042

Abstract: A universal serial bus (USB) extension allows for the transmission of data at high speeds over a much greater distance than typical USB operating range. USB devices (116-1, 116-2) may be connected to a host computer (102) at distances of 750 meters or more. USB tokens from a host computer (102) are spoofed.

Abstract translation: 通用串行总线（USB）扩展允许以比典型USB操作范围更远的距离高速传输数据。 USB设备（116-1,116-2）可以在750米或更远的距离处连接到主计算机（102）。 来自主机（102）的USB令牌被欺骗。

公开(公告)号：WO2007061432A1

公开(公告)日：2007-05-31

申请号：PCT/US2006/006477

申请日：2006-02-23

Applicant: VETRA SYSTEMS CORPORATION ,  ULENAS, Jonas

Inventor： ULENAS, Jonas

IPC: G06F13/14 ,  G06F15/173 ,  G09G5/00

CPC classification number: G06F13/4045 ,  G06F3/14 ,  G06F13/387

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing.

Abstract translation: 用于增强通用串行总线（USB）应用的系统包括上游处理器，下游处理器和主控制器。 上游处理器接受来自USB主机的标准USB信号，并在所需时间内独立提供USB规范所要求的响应。 可连接到USB兼容设备的下游处理器接受来自USB兼容设备的USB信号，并在所需时间范围内提供USB规范要求的响应。 主控制器互连上游和下游处理器，并提供上行和下行定时之间的时序独立性。

公开(公告)号：WO2003065581A1

公开(公告)日：2003-08-07

申请号：PCT/US2003/001804

申请日：2003-01-21

Applicant: SONICS, INC.

Inventor： EBERT, Jeffrey, A. ,  ROSSEEL, Geert ,  MEYER, Michael, J.

IPC: H03K19/0175

CPC classification number: G06F13/4045

Abstract: An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

Abstract translation: 公开了一种具有第一和第二总线的装置。 在一个实施例中，多个单元耦合到第一和第二总线。 单位包括中间单位和两个单位。 每个侧单元具有耦合到中间单元的第一总线输入的第一总线输出。 中间单元具有耦合到每个侧单元的第二总线输入的第二总线输出。

公开(公告)号：WO02075579A3

公开(公告)日：2003-03-27

申请号：PCT/US0203327

申请日：2002-02-04

Applicant: SUN MICROSYSTEMS INC

Inventor： QUAN TAI ,  SMITH BRIAN ,  LEWIS JAMES

IPC: G06F15/177 ,  G06F13/14 ,  G06F13/40 ,  G06F15/173

CPC classification number: G06F13/14 ,  G06F13/4031 ,  G06F13/4045

Abstract: A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Abstract translation: 一种包括耦合到第一中继器的第一中继器和第二中继器的计算机系统。 计算机系统还包括耦合到第一中继器的第三中继器。 第一中继器包含第一仲裁器，仲裁第一中继器和第二中继器之间的事务，并且仲裁第一中继器和第三中继器之间的事务。 第二中继器从第一中继器接收事务，并且包含预测从第一中继器接收到第二中继器的事务的第二仲裁器。