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    SIGNAL LINE DRIVE CIRCUIT AND LIGHT EMITTING DEVICE
    2.
    发明申请
    SIGNAL LINE DRIVE CIRCUIT AND LIGHT EMITTING DEVICE 审中-公开
    信号线驱动电路和发光装置

    公开(公告)号：WO03038796B1

    公开(公告)日：2003-09-25

    申请号：PCT/JP0211354

    申请日：2002-10-31

    Applicant: SEMICONDUCTOR ENERGY LAB ,  KIMURA HAJIME

    Inventor： KIMURA HAJIME

    IPC: G09G3/20 ,  G09G3/32 ,  G09G3/30 ,  G05F1/10

    CPC classification number: G09G3/325 ,  G09G3/2018 ,  G09G3/2022 ,  G09G3/3283 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/027 ,  G09G2320/0233

    Abstract: A technique for suppressing affect of irregularities of transistor characteristics in a signal line drive circuit. The signal line drive circuit includes a first current source circuit (431) arranged in a first latch (416) and a second current source circuit (432) arranged in a second latch (417), so as to correspond to each of signal lines. The first current source circuit has capacity means for converting the video signal current supplied from a video signal constant current source (109) into voltage according to the sampling pulse supplied from the shift register (415) and supply means for supplying current based on the converted voltage. The second current source circuit has capacity means for converting current supplied from the first latch into voltage and supply means for supplying current based on the converted voltage. Thus, current output is performed according to a video signal, not depending on the transistor characteristic.

    Abstract translation: 抑制信号线驱动电路中晶体管特性不规则的影响的技术。 信号线驱动电路包括布置在第一锁存器（416）中的第一电流源电路（431）和布置在第二锁存器（417）中的第二电流源电路，以便对应于每个信号线。 第一电流源电路具有用于根据从移位寄存器（415）提供的采样脉冲将从视频信号恒流源（109）提供的视频信号电流转换为电压的电容装置和用于根据转换的 电压。 第二电流源电路具有用于将从第一锁存器提供的电流转换成电压的电源装置和用于基于转换的电压提供电流的电源装置。 因此，根据视频信号执行电流输出，而不依赖于晶体管特性。

    GRAYSCALE STATIC PIXEL CELL FOR OLED ACTIVE MATRIX DISPLAY
    3.
    发明申请
    GRAYSCALE STATIC PIXEL CELL FOR OLED ACTIVE MATRIX DISPLAY 审中-公开
    用于OLED主动矩阵显示的灰度静态像素单元

    公开(公告)号：WO02017289A1

    公开(公告)日：2002-02-28

    申请号：PCT/US2001/025975

    申请日：2001-08-20

    IPC: G09G3/32

    CPC classification number: G09G3/3233 ,  G09G2300/0417 ,  G09G2300/0828 ,  G09G2300/0857

    Abstract: The grayscale data for OLED pixels in an active matrix display is stored as digital data in static memory cells of the display. The digital data is provided to current drivers that produce a current level that is proportional to the digital data and deliver grayscale levels to the OLED. The display does not require refreshing and is written to only when the data for pixels has changed.

    Abstract translation: 有源矩阵显示器中OLED像素的灰度数据作为数字数据存储在显示器的静态存储单元中。 数字数据被提供给当前驱动器，其产生与数字数据成比例的电流电平并且向OLED提供灰度级。 显示不需要刷新，只有当像素的数据发生变化时才会写入。

    DISPLAY
    4.
    发明申请
    DISPLAY 审中-公开
    显示

    公开(公告)号：WO01073737A1

    公开(公告)日：2001-10-04

    申请号：PCT/JP2001/002792

    申请日：2001-03-30

    IPC: G02F1/1362 ,  G09G3/20 ,  G09G3/32 ,  G09G3/36 ,  G09G3/30 ,  G02F1/133

    CPC classification number: G09G3/2014 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2203/30 ,  G09G3/2074 ,  G09G3/3607 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0857 ,  G09G2320/0276

    Abstract: Provided in an array pattern of a dot, which is a minimum unit of display, are n sets of a storage circuit that holds an image signal by using connected write and data lines out of the write and data lines laid corresponding to the array pattern, an electrooptic element operating depending on supplied electric power, and an active element for controlling the electrooptic element. The n sets have the same shape and can express 2 levels of gray scale. Electric power the magnitude of which depends on the value of a bit represented by an image signal stored in the storage circuit is supplied to each set.

    Abstract translation: 以作为显示的最小单位的点的阵列图案提供的是n组存储电路，其通过使用与阵列图案相对应的写入和数据线中的连接的写入和数据线保持图像信号， 根据提供的电力来操作的电光元件以及用于控制电光元件的有源元件。 n组具有相同的形状，并且可以表达2 等级的灰度级。 电力的大小取决于由存储在存储电路中的图像信号所表示的位的值被提供给每一组。

    DISPLAY DEVICE
    8.
    发明申请
    DISPLAY DEVICE 审中-公开
    显示设备

    公开(公告)号：WO2009064352A1

    公开(公告)日：2009-05-22

    申请号：PCT/US2008/012297

    申请日：2008-10-30

    Applicant: EASTMAN KODAK COMPANY ,  KAWABE, Kazuyoshi

    Inventor： KAWABE, Kazuyoshi

    IPC: G09G3/32

    CPC classification number: G09G3/3275 ,  G09G3/2022 ,  G09G3/2081 ,  G09G3/3233 ,  G09G3/3258 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2310/027 ,  G09G2330/021 ,  G09G2330/023 ,  G09G2360/12

    Abstract: To reduce the number of sub-frames and perform high resolution display with low power consumption, each of the pixels has a digital emission period Td and an analog emission period Ta, and is driven in a time-divided fashion in a digital manner or in an analog manner. Each of the pixels performs high resolution display when being driven in an analog manner, and performs display with low power consumption when being driven in a digital manner.

    Abstract translation: 为了减少子帧的数量并以低功耗执行高分辨率显示，每个像素具有数字发射周期Td和模拟发射周期Ta，并且以数字方式或时间分割的方式驱动 模拟方式。 当以模拟方式驱动时，每个像素执行高分辨率显示，并且以数字方式驱动时以低功耗进行显示。

    DIGITAL DRIVE ARCHITECTURE FOR FLAT PANEL DISPLAYS
    9.
    发明申请
    DIGITAL DRIVE ARCHITECTURE FOR FLAT PANEL DISPLAYS 审中-公开
    平板显示器的数字驱动架构

    公开(公告)号：WO2006128069A3

    公开(公告)日：2007-12-13

    申请号：PCT/US2006020630

    申请日：2006-05-25

    Applicant: NUELIGHT CORP ,  NAUGLER W EDWARD ,  FRANK MICHAEL ,  BASSETTI CHESTER FLOYD

    Inventor： NAUGLER W EDWARD ,  FRANK MICHAEL ,  BASSETTI CHESTER FLOYD

    IPC: G06F3/038

    CPC classification number: G09G3/2011 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/3648 ,  G09G2300/0814 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2360/148

    Abstract: The present invention describes a new digital drive concept for flat panel displays (LCD) where an all-digital drive is used to write data to pixels, which establish the gray scale for each pixel. In addition th einvention integtates the all-digital drive with an optical sensor feedback circuit in the pixel without having to add an extra data line for the pixel sensor. Also discussed is a novel unique puls timing system, where the postioning of the pulse in time has 12 bit accuracy using 8 bit grayscale data and a phase delay system (delay locked loop, DLL).

    Abstract translation: 本发明描述了一种用于平板显示器（LCD）的新的数字驱动器概念，其中使用全数字驱动器将数据写入像素，其建立每个像素的灰度级。 此外，全息数字驱动器与像素中的光学传感器反馈电路相结合，无需为像素传感器添加额外的数据线。 还讨论了一种新颖的独特的脉冲定时系统，其中使用8位灰度数据和相位延迟系统（延迟锁定环，DLL）在时间上放置脉冲具有12位精度。

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