公开(公告)号：WO1981002652A1

公开(公告)日：1981-09-17

申请号：PCT/FI1981000017

申请日：1981-03-11

Applicant: LEPPAEVUORI S ,  RAPELI J

IPC: H03H07/06

CPC classification number: H01C10/16 ,  H01C17/23 ,  H01L27/016 ,  H03H1/02 ,  Y10T29/49099

Abstract: A uniform electric component realizing a resistive-capacitive impedance, or a stub, comprising such a parallel connection of shorted and open structures of various lengths and widths of distributed RC-structures, where different structures are manifested as a steplike or smoothened shape of the line opposite the driving point of the component. The structures are also manifested as a mutual electric connection or disconnection between the resistor layer (13) and the ground plane (221) at various points of the said line. The measures of the stub are defined in a successive iteration process between the employed frequencies (f u, f u...) and the required admittances (Y u, Y u...). The stub is trimmed by shortening it or by removing or disconnecting one or more layers so that the endline of the remaining structure becomes perpendicular to the conduction band (211). The stub can also be manufactured as a reversibly trimmable structure. The stub can be used as part of a bandrejection filter.

Abstract translation: 实现电阻电容阻抗的均匀电气部件或短截线包括分布式RC结构的各种长度和宽度的短路和开放结构的并联连接，其中不同的结构表现为线的阶梯状或平滑形状 与组件的驱动点相反。 这些结构也表现为在所述线的各个点处的电阻层（13）和接地平面（221）之间的互电连接或断开。 在所使用的频率（f u，u u，u u）之间的连续迭代过程和所需的导纳（Y u，Y u，...）之间的连续迭代过程中定义了短截线的度量。 ）。 通过缩短或者通过去除或断开一个或多个层来修剪短截线，使得剩余结构的终端线垂直于导带（211）。 短截线也可以制造成可逆的可调节结构。 短截线可用作带状滤波器的一部分。

公开(公告)号：WO99005786A1

公开(公告)日：1999-02-04

申请号：PCT/US1998/009816

申请日：1998-05-14

IPC: H01G4/40 ,  H03H1/02 ,  H03H7/06

CPC classification number: H03H1/02 ,  H03H2001/0085

Abstract: Composite RC devices provide predetermined impedance properties in a package similar to multilayer ceramic capacitors of the prior art. The RC devices (10) include a plurality of first and second ceramic layers (32) interleaved to form a stack. The ceramic layers each include a suitable electrode structure (28, 30) of opposite polarity forming the equivalent of multiple two-plate capacitors. One or more resistors (34, 36) are embedded in the device body and are selectively connected to the capacitor structure. In some presently preferred embodiments, multiple parallel resistors (34, 36) are provided, such as on each electrical side of the capacitor structure.

Abstract translation: 复合RC器件在类似于现有技术的多层陶瓷电容器的封装中提供预定的阻抗特性。 RC装置（10）包括交织以形成堆叠的多个第一和第二陶瓷层（32）。 陶瓷层各自包括相反极性的合适的电极结构（28,30），形成多个双层电容器的等效物。 一个或多个电阻器（34,36）嵌入在器件主体中并且选择性地连接到电容器结构。 在一些当前优选的实施例中，提供多个并联电阻器（34,36），例如在电容器结构的每个电气侧。

公开(公告)号：WO2014091534A1

公开(公告)日：2014-06-19

申请号：PCT/JP2012/081906

申请日：2012-12-10

Applicant: 松江エルメック株式会社

Inventor： 亀谷　雅明

IPC: H04L25/03

CPC classification number: H03H1/02 ,  H03H21/0001 ,  H04B3/04 ,  H04B3/14 ,  H04B7/005 ,  H04L25/03 ,  H04L25/03878

Abstract: 　 【課題】　高速シリアル伝送において、伝送損失を受けて振幅差が発生したデータ信号の振幅を均等化する。 【解決手段】　第１の誘電体層９Ａの片面には、一端が信号入力位置となり、他端が第１の終端抵抗５Ａに接続された第１のミアンダ線路１Ａを形成する。第１の誘電体層９Ａとの対面側に、第１のミアンダ線路１Ａに対面する第２のミアンダ線路１Ｃを形成する。第２のミアンダ線路１Ｃは、一端が第１のミアンダ線路１Ａの他端側に位置して信号出力位置となり、他端が第２の終端抵抗５Ｃに接続する。第１の誘電体層９Ａと対面する側に第１の導線路３Ａを形成する。第１の導線路３Ａは、一端を信号入力位置に、他端を信号出力位置に接続する。第１の導線路３Ａ途中の分断区間を第１の直列抵抗７Ａで結ぶ。

Abstract translation: [问题]为了均衡由高速串行传输中的传输损失引起的振幅差产生的数据信号的幅度。 第一介电层（9A）的一个表面形成有第一曲折线（1A），其一端处于信号输入位置，另一端连接到第一终端电阻（5A） 。 面向第一曲折线（1A）的第二曲折线（1C）形成在面对第一介电层（9A）的一侧上。 第二曲折线（1C）的一端位于第一曲折线（1A）的另一端，以便处于信号输出位置，另一端连接到第二终端电阻（5C）。 第一导体线（3A）形成在面对第一介电层（9A）的一侧。 第一导线（3A）的一端连接在信号输入位置，另一端连接在信号输出位置。 在第一导体线的中间的分隔部分由第一串联电阻器（7A）连接。

公开(公告)号：WO2007118167A3

公开(公告)日：2008-01-31

申请号：PCT/US2007066097

申请日：2007-04-05

Applicant: QUALCOMM INC ,  CICALINI ALBERTO

Inventor： CICALINI ALBERTO

IPC: H03H1/02

CPC classification number: H03H1/02 ,  H03H2210/021 ,  H03H2210/043

Abstract: A two-step tuning process for resistors (410) and capacitors (420) in an integrated circuit (170) is described. In the first step of the tuning process, an on-chi? adjustable resistor (410) is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate within a target percentage determined by the external resistor and the design of the adjustable resistor (410). In the second step, an adjustable capacitor (420) is tuned based on the value of the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor (420) may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate within a target percentage determined by the accurate clock and the design of the adjustable capacitor (420). The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

Abstract translation: 描述了集成电路（170）中的电阻器（410）和电容器（420）的两步调整过程。 在调整过程的第一步，一个on-chi？ 基于外部电阻器调节可调电阻器（410）以获得调谐电阻器。 调谐电阻的值在由外部电阻和可调电阻（410）的设计确定的目标百分比内是准确的。 在第二步骤中，基于调谐电阻器的值和准确的时钟调整可调电容器（420），以获得具有准确值的调谐电容器。 可调谐电容器420可以被调谐成使得调谐电阻器和调谐电容器的RC时间常数在由可调电容器（420）的精确时钟和设计确定的目标百分比内是准确的。 可以分别基于调谐电阻器和调谐电容器来调整集成电路上的其它电路的电阻器和电容器。

公开(公告)号：WO2007118167A2

公开(公告)日：2007-10-18

申请号：PCT/US2007/066097

申请日：2007-04-05

Applicant: QUALCOMM INCORPORATED ,  CICALINI, Alberto

Inventor： CICALINI, Alberto

CPC classification number: H03H1/02 ,  H03H2210/021 ,  H03H2210/043

Abstract: A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

Abstract translation: 描述了集成电路中的电阻器和电容器的两步调谐过程。 在调谐过程的第一步中，基于外部电阻器调整片上可调电阻以获得调谐电阻。 调谐电阻的值精确到由外部电阻确定的目标百分比和可调电阻的设计之内。 在第二步中，基于调谐电阻器和精确时钟来调节可调电容器以获得具有准确值的调谐电容器。 可调整的可调电容器可以使得调谐电阻器和调谐电容器的RC时间常数精确到由精确时钟和可调电容器的设计确定的目标百分比之内。 可以分别基于调谐电阻器和调谐电容器来调整集成电路上的其它电路的电阻器和电容器。

公开(公告)号：WO2006104671A1

公开(公告)日：2006-10-05

申请号：PCT/US2006/008741

申请日：2006-03-10

Applicant: FREESCALE SEMICONDUCTOR ,  ROTCHFORD, Chris, J. ,  COPOLILLO, Clement, R.

Inventor： ROTCHFORD, Chris, J. ,  COPOLILLO, Clement, R.

IPC: H03B1/00 ,  H03K5/00 ,  H04B1/10

CPC classification number: H03H1/02 ,  H03H2210/043 ,  H03J2200/10

Abstract: Methods and apparatus are provided for tuning out time constant deviations of a network (414) due to process, voltage, and temperature variations. The apparatus (400) 5 comprises a clock reference (404) from which a digital time constant is correlated to the nominal time constant of the network (414). The correlated digital time constant is applied to the network (414), and the output charge/discharge waveform swing is compared to a predetermined reference voltage. If the charge/discharge waveform swing does not match the reference voltage, an offset signal is generated. The offset signal is applied to a control circuit (402) that generates a corresponding tuning signal. The tuning signal is applied to the network (414) to adjust the internal components incrementally until a match is achieved. The apparatus (400) can be configured as a built-in self -test digital time constant tracking circuit, and can be integrated with the network (414) on an IC chip.

Abstract translation: 提供了方法和装置，用于调节由于过程，电压和温度变化引起的网络（414）的时间常数偏差。 装置（400）5包括时钟参考（404），数字时间常数与网络的标称时间常数相关联（414）。 将相关数字时间常数施加到网络（414），并将输出充电/放电波形摆动与预定参考电压进行比较。 如果充电/放电波形摆幅与参考电压不匹配，则产生偏移信号。 偏移信号被施加到产生相应调谐信号的控制电路（402）。 调谐信号被施加到网络（414）以递增地调整内部组件，直到达到匹配。 该装置（400）可以被配置为内置的自测数字时间常数跟踪电路，并且可以与IC芯片上的网络（414）集成。

公开(公告)号：WO2005002021A1

公开(公告)日：2005-01-06

申请号：PCT/KZ2003/000006

申请日：2003-11-27

IPC: H02J3/01

CPC classification number: H02M1/126 ,  H02M1/44 ,  H03H1/02

Abstract: The inventive supply-line filter relates to electrical engineering, in particular to filters for suppressing and eliminating high-frequency electromagnetic componenets in a power alternating-current circuit. Said invention makes it possible to essentially reduce the amplitude of a high-frequency electromagnetic voltage component within a frequency range of 1-100 kHz, and to simplify the filter design and reduce the size thereof. Said technical result is achieved by said supply-line filter which comprises a capacitor and a resistor which are embodied in the form of a non-inductive thin-film capacitor and a resistor in parallel connected thereto. A capacitor whose capacity ranges from 5 to 30 mu F and a resistor whose resistance ranges from 20 to 100 k OMEGA are used.

Abstract translation: 本发明涉及电气工程领域，尤其涉及用于去除和消除工业频率交流电路中的高频电磁部件的滤波器。 本发明的目的是显着降低1至100kHz频率范围内的高频电磁电压分量的幅度，并简化滤波器的设计并减小滤波器的尺寸。 为此，应该使用包括电容器和电阻器的本发明的电源滤波器。 在这个滤波器中使用了一个并联电阻的非感性薄膜电容。 另外，该滤波器最好使用容量为5至30μF的电容器和电阻为20至100kΩ的电阻器。

公开(公告)号：WO2004079914A1

公开(公告)日：2004-09-16

申请号：PCT/EP2003/002371

申请日：2003-03-07

Applicant: FUJITSU LIMITED ,  MARTON, Walter

Inventor： MARTON, Walter

IPC: H03L7/107

CPC classification number: H03H1/02 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/18

Abstract: A PLL circuit comprising a loop filter with at least a first and a second bandwith is provided. The first bandwith of the loop filter is determined by a first network of circuit components and used out of the linear rangs of the PLL circuit and the second bandwith is determined by a second network of circuit components and used within the linear range of the PLL circuit. A node of said second network is charged to a voltage level given by a node of said first network while the second network is switched off. When the second network is switched in, no long lasting charging process is required. Therefore, the lock time of the PLL circuit is reduced.

Abstract translation: 提供一种PLL电路，其包括具有至少第一和第二带通的环路滤波器。 环路滤波器的第一频带由电路组件的第一网络确定，并且在PLL电路的线性范围之外使用，并且第二频带由第二电路组件网络确定并且在PLL电路的线性范围内使用 。 所述第二网络的节点被充电到由所述第一网络的节点给出的电压电平，而所述第二网络被关闭。 当第二个网络被切换时，不需要持续的充电过程。 因此，PLL电路的锁定时间减少。

公开(公告)号：WO1987006405A1

公开(公告)日：1987-10-22

申请号：PCT/FR1987000117

申请日：1987-04-10

Applicant: THOMSON SEMICONDUCTEURS ,  RAMET, Serge

Inventor： THOMSON SEMICONDUCTEURS

IPC: H03H11/12

CPC classification number: H03H1/02 ,  H03H11/1204

Abstract: A low-pass filtering cell uses a resistive line with distributed capacity (LR) having an intermediary plug (P) to which there is connected a looping capacitor (C1), the resistive line being connected to the input of an operational amplifier (A). The intermediary plug is located at one third of the length of the line in order to minimize the global size of the cell while obtaining a response curve which is as flat as possible.

Abstract translation: 低通滤波单元使用具有中间插头（P）的分布容量（LR）的电阻线，其中连接有环路电容器（C1），该电阻线路连接到运算放大器（A）的输入端， 。 中间塞子位于线的长度的三分之一处，以便最小化单元的全局尺寸，同时获得尽可能平坦的响应曲线。

公开(公告)号：WO2016093991A1

公开(公告)日：2016-06-16

申请号：PCT/US2015/059451

申请日：2015-11-06

Applicant: QUALCOMM INCORPORATED

Inventor： TAGHIVAND, Mazhareddin ,  RAJAVI, Yashar ,  KHALILI, Alireza

IPC: H03H11/24

CPC classification number: H03K5/08 ,  H03H1/02 ,  H03H11/245

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor 210, 220 having a gate, a source connected with a first node 214 of the circuit, and a drain connected with a second node 216 of the circuit. The circuit may also include a voltage-limiting device 224, 226 connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor 212, 222 configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract translation: 本公开的某些方面通常涉及产生大的电阻。 一个示例电路通常包括具有栅极的第一晶体管210,220，与电路的第一节点214连接的源极以及与该电路的第二节点216连接的漏极。 电路还可以包括连接在第一晶体管的栅极和源极之间的电压限制器件224,226，其中如果正向偏置，器件被配置为限制第一晶体管的栅极 - 源极电压，使得 第一晶体管在子阈值区域中工作。 该电路还可包括第二晶体管212,222，其被配置为用电流偏压限压器件，其中第二晶体管的漏极与第一晶体管的栅极连接，第二晶体管的栅极与 第一节点，并且第二晶体管的源极与电势连接。