公开(公告)号：WO2021201344A1

公开(公告)日：2021-10-07

申请号：PCT/KR2020/009489

申请日：2020-07-17

Applicant: 쿠팡 주식회사

Inventor： 김영진 ,  이진수 ,  우수지 ,  안석민

IPC: G06F11/34 ,  G06Q30/06 ,  G06F11/3471 ,  G06F11/3476 ,  G06F16/9566 ,  G06Q30/0601 ,  H04L67/02 ,  H04L67/22 ,  H04L67/303

Abstract: 복수의 전자 장치에 의해 접근 가능한 복수의 도메인을 포함하는 시스템을 상기 복수의 전자 장치 중 적어도 하나에 제공하는 단계와, 상기 복수의 도메인 중 상기 시스템의 컴포넌트에 대한 입력이 확인되는 도메인 또는 상기 복수의 도메인 중 URL(uniform resource locator)의 적어도 일부가 변경되는 도메인에 대한 사용 로그 데이터(usage log data)를 상기 복수의 전자 장치 중 적어도 하나로부터 획득하는 단계와, 상기 획득된 사용 로그 데이터를 기초로, 상기 시스템의 통합 사용 로그 데이터를 생성하는 단계를 포함하는 서버의 동작 방법 및 그 서버를 제공한다.

公开(公告)号：WO2023057733A1

公开(公告)日：2023-04-13

申请号：PCT/GB2022/052096

申请日：2022-08-11

Applicant: ARM LIMITED

Inventor： WILLIAMS, Michael John

IPC: G06F11/34 ,  G06F11/30 ,  G06F11/36 ,  G06F11/302 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/865 ,  G06F9/30101

Abstract: An apparatus comprises reset circuitry to perform a cold reset and to perform a warm reset by resetting a subset of state that is reset the cold reset, and branch recording circuitry to perform branch recording to store, in branch record storage circuitry, information about processed branch instructions. The branch recording circuitry determines whether warm and cold branch recording configuration values held in at least one register satisfy a predetermined condition; and when the warm and cold branch recording configuration values fail to satisfy the predetermined condition, branch recording is disabled. The branch record storage circuitry is configured to make the information about the processed branch instruction available for diagnostic analysis. The cold reset comprises resetting both of the warm and cold branch recording configuration values, and the warm reset comprises resetting the warm branch recording configuration value and leaving the cold branch recording configuration value unchanged.

公开(公告)号：WO2021226012A2

公开(公告)日：2021-11-11

申请号：PCT/US2021/030552

申请日：2021-05-04

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： MOLA, Jordi

IPC: G06F11/34 ,  G06F11/36 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/3636 ,  G06F2201/885

Abstract: Reducing overheads of recording a replayable execution trace of a program's execution at a computer processor by omitting logging of accesses to memory addresses whose values can be reconstructed or predicted. A computer system determines that memory values corresponding to a range of memory addresses within a memory space for a process can be obtained separately from the process' execution, and configures a data structure for instructing a processor to omit logging of memory accesses when the processor accesses an address within this range while executing the process. Correspondingly, upon detecting a memory access while executing the process, the processor determines if it has been instructed to omit logging of the access by checking the data structure. When the data structure instructs the processor to omit logging of the access, the processor omits logging the memory access while it uses a cache to process the memory access.