公开(公告)号：WO2022271267A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/026385

申请日：2022-04-26

Applicant: XILINX, INC.

Inventor： POPE, Steven Leslie ,  ROBERTS, Derek Edward ,  KITARIEV, Dmitri ,  TURTON, Neil Duncan ,  RIDDOCH, David James ,  SOHAN, Ripduman

IPC: G06F13/16 ,  G06F13/1621 ,  G06F13/1642 ,  G06F13/1678 ,  G06F13/287 ,  G06F13/385 ,  G06F2213/3808 ,  G11C7/1069 ,  G11C7/1096

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.